Feedforward Path Research Articles

Dynamic Cross-Task Representation Adaptation for Clinical Targets Co-Segmentation in CT Image-Guided Post-Prostatectomy Radiotherapy.

Adjuvant and salvage radiotherapy after radical prostatectomy requires precise delineations of prostate bed (PB), i.e., the clinical target volume, and surrounding organs at risk (OARs) to optimize radiotherapy planning. Segmenting PB is particularly challenging even for clinicians, e.g., from the planning computed tomography (CT) images, as it is an invisible/virtual target after the operative removal of the cancerous prostate gland. Very recently, a few deep learning-based methods have been proposed to automatically contour non-contrast PB by leveraging its spatial reliance on adjacent OARs (i.e., the bladder and rectum) with much more clear boundaries, mimicking the clinical workflow of experienced clinicians. Although achieving state-of-the-art results from both the clinical and technical aspects, these existing methods improperly ignore the gap between the hierarchical feature representations needed for segmenting those fundamentally different clinical targets (i.e., PB and OARs), which in turn limits their delineation accuracy. This paper proposes an asymmetric multi-task network integrating dynamic cross-task representation adaptation (i.e., DyAdapt) for accurate and efficient co-segmentation of PB and OARs in one-pass from CT images. In the learning-to-learn framework, the DyAdapt modules adaptively transfer the hierarchical feature representations from the source task of OARs segmentation to match up with the target (and more challenging) task of PB segmentation, conditioned on the dynamic inter-task associations learned from the learning states of the feed-forward path. On a real-patient dataset, our method led to state-of-the-art results of PB and OARs co-segmentation. Code is available at https://github.com/ladderlab-xjtu/DyAdapt.

Multi‐Stage CMOS OTA Frequency Compensation: Genetic algorithm approach

AbstractMultistage amplifiers have become appropriate choices for high‐speed electronics and data conversion. Because of the large number of high‐impedance nodes, frequency compensation has become the biggest challenge in the design of multistage amplifiers. The new compensation technique in this study uses two differential stages to organize feedforward and feedback paths. Five Miller loops and a 500‐pF load capacitor are driven by just two tiny compensating capacitors, each with a capacitance of less than 10 pF. The symbolic transfer function is calculated to estimate the circuit dynamics and HSPICE and TSMC 0.18 μm. CMOS technology is used to simulate the proposed five‐stage amplifier. A straightforward iterative approach is also used to optimize the circuit parameters given a known cost function. According to simulation and mathematical results, the proposed structure has a DC gain of 190 dB, a gain bandwidth product of 15 MHz, a phase margin of 89°, and a power dissipation of 590 μW.

High power flatness and wide spectrum range microwave frequency combs generation based on an actively mode-locked optoelectronic oscillator with intensity feed-forward path

An actively mode-locked optoelectronic oscillator (OEO) with intensity feed-forward path is proposed and experimentally demonstrated to generate microwave frequency combs (MFCs) with high power flatness and wide spectrum range. An intensity feed-forward path with the same time delay as the delay of the main loop is inserted into an actively mode-locked OEO, which optimizes the power flatness and spectrum range of the generated MFCs signal. Experimental results show that comb lines within ± 10 dB power variations increase from 15 to 78 and power difference decreases from 8.2 dB to 1.5 dB when the intensity feed-forward path is working in the loop. Moreover, the performance of single sideband (SSB) phase noise with different lengths of SMF inserted in the proposed scheme are also investigated.

Novel anti-disturbance fast terminal sliding mode control with improved quick reaching law for DC-DC buck converter

In order to improve the performance and suppress the chattering problem of variable structure control system, a nonlinear novel quick reaching law with dynamic power term is suggested, which could enhance the convergence rate whenever the system state position is near to or far from the manifold. Furthermore, a novel fast terminal sliding surface with additional nonlinear terms is developed and designed. The combination of these structure propositions can minimize both the reaching time and sliding time convergence. The finite-time stability of the proposed control paradigm is demonstrated via the Lyapunov criteria method. Moreover, in order to see the superior performance of the compound control, a disturbed DC-DC buck converter is selected as plant in this work. In addition, the extended state observer is designed and added in feedforward path of control law of sliding mode structure. In order to estimate the unknown uncertainties, the results demonstrate that the nonlinear novel fast terminal sliding mode with variable quick reaching law brings the system at equilibrium point more rapidly than the traditional manifolds and reaching laws. More than that, the closed-loop system performance has better transient response, lower steady state error and lesser sensitivity to disturbances.

On the Synthesis of Continuous-Time Sturdy MASH Delta-Sigma Modulators

Sturdy multi-stage noise-shaping (SMASH) delta-sigma modulators (DSMs) achieve high-order noise-shaping while significantly alleviating the mismatch issue between analog and digital transfer functions. Based on the SMASH architecture, we propose a methodology of synthesizing its continuous-time (CT) architecture from its discrete-time (DT) counterpart by using loop-filter connections. The proposed methodology circumvents the necessity of a direct extraction of the quantization noise from the early stages, which is problematic for CT architectures with high sampling rate. Moreover, the proposed method allows to intuitively compensate the CT SMASH for the excess loop delay (ELD). Furthermore, an input feedforward path is introduced into the second stage to eliminate the STF peaking induced by the ELD. A 2–2 SMASH topology is analyzed as a case study to demonstrate the synthesis methodology. Besides, we present derivations for determining loop-filter coefficients. Simulation results confirm the efficacy of the synthesis methodology for the SMASH topology.

V-Iq Based Control Scheme for Mitigation of Transient Overvoltage in Distribution Feeders With High PV Penetration

High penetration of rooftop photovoltaic (PV) systems in distribution feeders can give rise to overvoltage during peak generation hours. A well-known solution for this problem is Volt-VAR control method, in which PV inverters mitigate the overvoltage by reactive power absorption. The conventional Volt-VAR scheme calculates the reactive power reference based on a limited bandwidth V-Q droop controller. Although the conventional method is capable of steady-state voltage regulation, it is not effective against voltage overshoots caused by fast solar irradiance variations. In this paper, a new V-Iq based Volt-VAR control scheme is presented to suppress the transient voltage overshoots during cloud passing. In this method, the bandwidth of the Volt-VAR controller is increased to enhance its responsiveness to voltage variations. To prevent instability caused by unwanted interaction between the high bandwidth Volt-VAR controller and the voltage feedforward section of the inner control loop, a low pass filter is added to the feedforward path. Small signal analysis of the proposed method provides a guideline for designing the bandwidths of Volt-VAR controller and feedforward filter. The stability of the proposed method is assessed based on Lyapunov method. Hardware in the Loop (HIL) experimental results are presented to validate the proposed scheme.

Low Frequency Current Ripple Suppression for Two-Stage Single-Phase Inverter Based on Impedance Editing

The instantaneous output power of the two-stage single-phase inverter pulsates at double-line frequency, generating a large amount of second harmonic current (SHC) in the front-end dc-dc converter and input dc source. The SHC is harmful to the system performance. To address the issue, a control strategy based on port-impedance editing, where inductor current feedforward (ICFF) and bus voltage feedforward paths are employed, is proposed to reduce the low frequency ripple in the article. Due to only bandpass filter employed in each feedforward path, the proposed control scheme is relatively easy to be implemented. Under the control strategy, the dc-bus port-impedance of dc-dc converter is increased rapidly at double-line frequency, while staying low impedance for other frequencies. What is more, different ICFF paths are taken into insight to obtain optimized path. Meanwhile, the small signal model of front-end dc-dc converter is established and the design principle of key parameters is provided for the derived control strategy. Furthermore, the dynamic response with bandwidth limitation is also discussed in this article. Finally, a two-stage single-phase inverter prototype was fabricated and tested. The experimental results verify the performance of the proposed strategy with SHC reduction.

Design of a high‐performance advanced phase locked loop with high stability external loop filter

For this task, an improved phase locked loop (PLL) was developed using a more sophisticated phase-frequency detector with multiband flexible dividers that provide enhanced frequency resolution, a better spectrum, and a better output signal. Great timing jitter was the problem for the old PLL designs because of the unbalanced frequency transfer function caused by the voltage-controlled oscillator and noise introduced by increases in supply voltage. A new design was suggested for the phase-frequency detector (PFD) such that PLL lock times are reduced while maintaining a low level of phase jitter. This way, they used fewer transistors, used less power, and had lower propagation holdup and smaller size compared to static PFDs. Additionally, forward ring voltage-controlled oscillator may improve the resolution of frequency and phase variation errors owing to supply noise by balancing driving force ratios in the feed-forward and feedback paths. Additionally, there is a dynamic sense flexible divider with several bands for separating special divisions (divide-by-47 and divide-by-48) that lacks a few extra flip-flops which save considerable power and improves the frequency difficulties of the multi-band divider. The advanced phase locked loop (ADPLL) has integrated phase and frequency errors, where the ADPLL excels. The supply noise is decreased by three reference clock cycles and the effect is that the measurement of jitter is better. Advanced Phase Locked Loop oscillates at frequencies ranging from 500 MHz to 4 GHz. A root mean square jitter of 1.29 ps is observed at 1 GHz. Our PLL is rated at 92.1-μW, with power used at 0.31 mW/GHz. The aim of this article is to design a 180 mm CMOS-based PLL circuit with a 400 MHz clock and a 0.65 V supply at a fast, dynamic phase frequency detector for resolution and stability.

A Nested Miller Compensation with a large feed-forward transconductor for capacitor-less flipped voltage follower low dropout regulator

In this paper, a capacitor-less flipped voltage follower (FVF) low dropout (LDO) regulator using nested miller compensation with a large feed-forward transconductor (NMCLFT) is presented. The LDO regulator is a dual-summing based three-stage high-gain structure and NMCLFT stabilizes the feedback loop for the load current ranges of 0 to 50 mA with load capacitances of 0 to 100 pF. This LDO regulator uses the multiple feed-forward paths which enhance the unity gain bandwidth (UGB) as well as the transient responses. The large feed-forward transconductor separates the non-dominant complex poles of nested miller compensation (NMC) into two simple poles and pushes one of the poles into high-frequency. It also provides a strong low-frequency left-half plane (LHP) zero and pushes right-half plane (RHP) zero of NMC into high-frequency and makes the multi-pole LDO regulator into a single-pole LDO for all the cases, from light load to heavy load with different load capacitor corners. The NMCLFT eliminates the minimum load current and minimum load capacitance constraints with improved transient response. The proposed LDO regulator achieves the settling time of 120 ns with the minimum edge time of 10 ns for the load current ranges of 0 to 50 mA and the load capacitance ranges of 0 to 100 pF. This LDO is implemented in 130 nm CMOS technology and it consumes a quiescent current of 63μA.

A fully dynamic third-order EF-CIFF noise-shaping SAR ADC with NTF zeros optimization and passive integration

In this paper, a third-order noise-shaping successive approximation register (NS-SAR) analog-to-digital converter (ADC) is proposed which is simple and fully dynamic. A passive integrator is utilized in the feed-forward (FF) path of a second-order NS-SAR ADC with 2nd-order error-feedback (EF) filter to reduce the effect of inband quantization and comparator noise. The integrator implements a passive gain of 4x to make up its loss arising from the charge sharing between the integrator and digital-to-analog converter capacitors at the integration phase. Another advantage of the proposed structure is employing a simple low noise and low power one-input pair comparator unlike many published NS-SAR ADCs which use a comparator with multi-input pairs leading to enhanced comparator input-referred noise and power consumption. In this work, the zeros of the noise transfer function are optimized to enhance inband noise suppression. The proposed ADC is designed at circuit level using 0.18 μm TSMC CMOS technology with Cadence Virtuoso tool. The oversampling ratio, sampling frequency, and bandwidth are 8, 2.5 MS/s, and 156.25 kHz, respectively. According to the detailed post-layout simulation results, the achieved signal-to-noise and distortion ratio of the simulated ADC is 83.1 dB with 70.3 µW power consumption from a 1.1 V supply.

Model-Based Closed-Loop Control for High-Power Current Source Rectifiers Under Selective Harmonic Elimination/Compensation PWM With Fast Dynamics

Selective harmonic elimination/compensation PWM (SHE/SHC-PWM) is widely used in current source rectifiers (CSRs) under normal/distorted grid conditions due to its best line current harmonic performance with reduced switching losses. However, due to the off-line nature of SHE/SHC-PWM that operates over fundamental frequency, its dynamic performance under closed-loop control is usually not satisfactory compared with the space-vector modulation or carrier-based PWM (CB-PWM) for CSR. To improve the closed-loop dynamics of CSR under SHE/SHC-PWM, a model-based closed-loop control scheme is proposed in this article. In case of transient when the dc current reference of CSR changes, the new input references of the SHE/SHC-PWM module, i.e., the modulation index and delay angle, are directly calculated and updated in real-time based on the mathematical model of CSR derived in this article. As a result, the dynamic performance for dc current tracking under closed-loop SHE/SHC-PWM operations can be improved greatly due to this added model-based feedforward path, while the conventional feedback controller is still adopted but only for steady-state error corrections. The application of the proposed method on back-to-back current source converter (CSC) motor drives is also introduced. Simulation and experimental results validate this proposed control for CSR with fast dynamics.

A 516 μW, 121.2 dB-SNDR, and 125.1 dB-DR Discrete-Time Sigma-Delta Modulator with a 20 kHz BW

This article proposed a discrete-time single-loop 3rd order 5-bit Sigma-Delta (ΣΔ) modulator for the audio applications. In this modulator, a feed forward path is used to relax the design requirement of amplifier, which can reduce integrator’s output swing. And a 5-bit asynchronous SAR ADC combined with analog summing is adopted to quantify the summation of feedforward signal and loop filter output, which can significantly reduce power consumption. In addition, chopper stabilization technique is used to alleviate the flicker noise introduced by the first integrator. To eliminate the nonlinearity introduced by multibit quantizer, an improved data weighted average algorithm calibration circuit is proposed. The proposed modulator is implemented in 130 nm technology with a 1.12 mm2 core area. Operating at a 2.56MS/s sampling rate, post layout simulation results show that the modulator realizes 121.2-dB SNDR and 125.1-dB DR in a 20 kHz signal bandwidth, it dissipating 516 μW from 1.5 V supply. It also achieves the energy efficiency, as demonstrated by a Schreier figure of merit (FoMS) of 197 dB.

Linear parameter-varying gain-scheduled preview-based robust attitude control design for a staring-mode satellite

It is challenging to precisely control the attitude of a satellite when performing a fast and large-angle maneuver, for instance, in the staring mode. To solve this issue, this paper investigates a gain-scheduled preview-based robust attitude control method in the framework of linear parameter-varying control theory. Firstly, the linear parameter-varying model of an observation satellite with large-angle rotations is developed by choosing the attitude angles as scheduling parameters to take the dynamics variation into consideration. In order to ease the implementation in practical engineering applications, the structure of the linear parameter-varying controller is in the form of modified proportional-integral-derivative control. To simultaneously satisfy the requirements of fast rotational speed and high dynamic tracking performance, a gain-scheduled proportional-integral-derivative controller is designed with the future information of desired attitude signals included in the feedforward path. The proposed controller is synthesized within the framework of H∞ robust control to enhance the robustness against inaccurate previewed information and external disturbances. The corresponding control synthesis condition is derived as an optimization problem with linear matrix inequality constraints. Monte Carlo simulation results demonstrate that the dynamic tracking accuracy of the proposed control algorithm can be guaranteed to be less than 0.01 deg in the face of fast large-angle commands, inaccurate previewed information and external disturbances.

Miller compensated four-stage OTA with Q-reduction for wide range of load capacitors

This paper proposes a four-stage miller compensated Operational Transconductance Amplifier (OTA) with Q-reduction. The multi-stage OTA is an ideal choice for the submicron CMOS technology. The main challenge in multi-stage OTA design with low quiescent current is the increased number of high impedance nodes. These high impedance nodes create stability issues. Usually, the multi-stage OTA requires the compensation capacitor in the order of pF which consumes more chip area; moreover, it reduces the bandwidth of the OTA. The proposed four-stage OTA uses a single miller capacitor Cm along with a feed-forward capacitor Cf. The four-stage OTA uses only 500fF of total compensation capacitors to stabilize a complex four-stage OTA. The proposed OTA uses multiple feed-forward paths to enhance the small-signal and the large-signal performances of the OTA. The four-stage OTA achieves a better transient response with the settling time of 510ns under low quiescent power of 63.6μW for the wide range of load capacitors of 5pF to 100pF.

Agile offset frequency locking for single-frequency fiber lasers

Single frequency fiber lasers (SFFLs) have seen increasing applications in state-of-the-art quantum technologies, which usually require precise and stable offset frequency locking (OFL). However, limited by the piezoelectric transducer bandwidth in SFFLs and the loop bandwidth of the OFL, the large-gap jumping between two locked offset frequencies will take an undesirable amount of time. In order to diminish that consuming time, we developed an agile offset frequency locking system based on a hybrid loop of a feed-forward path and a feedback path. In accordance with the experimental demonstration, we characterized the performances of the offset frequency locking system, as frequency-locking stability with an Allan deviation of 3.2 × 10−14 at 1 s averaging time and jumping agility with a duration of 0.6 ms at 1.3 GHz frequency gap, which is a factor of 60 faster than that without the feed-forward path. This mechanism can find direct applications in existing quantum metrology experiments with SFFLs where high-speed frequency jumping or sweeping is needed.

Phase Feedforward Damping Control Method for Virtual Synchronous Generators

Damping control plays an important role in suppressing the oscillation modes of virtual synchronous generators (VSGs). The most widely used damping control method through a frequency deviation feedback path is confronted with multiple challenging inherent contradictions among the different control objectives, resulting in seriously degraded control performance of VSGs. To resolve these contradictions fundamentally, this article proposes a novel phase feedforward damping (PFD) control method for VSG from the perspective of restructuring the damping controller. It replaces the traditional frequency deviation feedback path with a novel damping controller utilizing a phase feedforward path. Then, considering the grid-connected and islanding operation modes, respectively, a detailed comparative study of the traditional damping-based VSG (Tra-VSG) and the PFD-based VSG (PFD-VSG) is conducted. Both the theoretical and experimental results demonstrate convincingly that the proposed PFD control method can reconcile the different control objects of VSG, and thus, compared with Tra-VSG, PFD-VSG exhibits vastly superior response performance of the active power and the frequency in both grid-connected and islanding operation modes.

A high-efficiency feedforward compensation method for capacitor-less LDO

This paper proposes a new structure of compensation for LDO. A feedforward path is added to this system and the gain of this feedforward stage is well-controlled by using the proposed structure so that it can accurately change the position of the zero generated by this system for accurate frequency compensation. The structure substantially improves stability at low power consumption, so that this structure implements a high-efficiency compensation method. This LDO is under SMIC 0.18μm CMOS process with a total area of 0.031 mm2. When the load current is 20 mA, the line regulation can be as low as 0.33 mV/V. The phase margin of proposed LDO can reach around 90 deg and the recovery time is less than 2μs. It is worth mentioning that the total quiescent current consumption of proposed LDO is only 6.58 μA and the current efficiency is above 99.94%.

A comparative research of innovative comparators

This paper studies four novel design comparators and gives a detailed analysis and summary of them. edge-pursuit comparator (EPC) improved energy efficiency and noise over conventional comparators by a circuit loop consisting of numbers of delay units. The triple-tail fully dynamic comparator minimizes the comparator’s total delay time and enhances the sample rate. The dynamic bias architecture of the double-tail latch-type comparator can provide a relatively high voltage gain while ensuring a low power consumption by stabilizing the static operating point. It also has advantages over conventional comparators in noise and delay. A triple-latch feedforward (TLFF) comparator improves on the triple-tail fully dynamic comparator. The triple-latch feedforward (TLFF) dynamic comparator consists of three-stage latches and a parallel feedforward path. It has a smaller delay time than other circuit designs, especially for large differential input signals.

Research on Four Different Designs of Comparator

Abstract Comparators contribute a significant role to analogue to digital converters (ADC). This paper describes and evaluates four excellent comparator optimisation schemes in recent years and analyses their advantages and disadvantages, providing ideas for the following comparator research direction. In addition, this paper introduces the design steps of each comparator optimisation scheme. It shows how the designer completes the final optimisation scheme step by step from the practical problems, which provides a specific reference for the comparator designers in the future. A double-tail latch-type comparator with dynamic bias adds a tail capacitor to the pre-amplifier to achieve low noise and high gain. Furthermore, a triple-tail dynamic comparator addresses a cascoded integrator. The new stage defines and attenuates the noise to achieve high speed and low noise. Compared to the triple-tail comparator, another design of a three-stage comparator is through adding a feedforward path between the first amplifier/latch and third latch to construct a triple-latch feedforward dynamic comparator. It is aimed to reduce delay and get low consumption in the region of the high voltage signal. Moreover, Edge-Pursuit Comparator (EPC) uses NAND gates and inverter delay cells to generate the comparison result between two input signals. Its circuit structure allows input noise tunability, automatic energy scaling, and low voltage tolerance.

Soft pneumatic actuators adapted in multiple environments: A novel fuzzy cascade strategy for the dynamics control with hysteresis compensation

Soft pneumatic actuators (SPAs) have been widely used in the design of various soft robots due to their compliance, adaptability, and high force density characteristics. However, it is a challenge to accurately model and control such soft pneumatic robotic systems due to inherent hysteresis nonlinearity, uncertainties, and disturbances from external environments. In this paper, we propose a novel fuzzy cascade strategy to control the dynamics of bellow-type soft pneumatic actuators when working in multiple environments (air, water, and their transition process). First, the components of the soft pneumatic system including the actuator and solenoid valve are mathematically modeled using second-order transfer functions, which are derived with a system identification method. Then, the Prandtl-Ishlinskii (P-I) model is proposed to accommodate and characterize the complex hysteresis effect. In the P-I model, the parameters are identified and derived using a particle swarm optimization (PSO) method. Subsequently, an inverse P-I model is constructed and placed in the feed-forward path to compensate for the hysteresis effect. In addition to the hysteresis nonlinearity, the uncertainties and disturbances from multiple environments will also degrade the tracking performance of soft pneumatic actuators. To enhance the adaptability, especially during the trans-environment process (e.g., from air into water or the reverse), a single-input FUZZY P+ID controller is proposed and integrated into the cascade strategy aiming to improve the robustness and precisely control the system dynamics. Extensive simulations and real-world tracking experiments of soft pneumatic actuators fabricated with the fused deposition modeling (FDM) method are performed to evaluate the performance of the proposed strategy and three designed controllers (PID, fuzzy PID, and FUZZY P+ID). It is noted that the comparison of tracking results has proved that the proposed FUZZY P+ID controller with only single input has better overall performance than traditional PID and fuzzy PID controllers in terms of adaptability and robustness.