A comparative research of innovative comparators

Abstract

This paper studies four novel design comparators and gives a detailed analysis and summary of them. edge-pursuit comparator (EPC) improved energy efficiency and noise over conventional comparators by a circuit loop consisting of numbers of delay units. The triple-tail fully dynamic comparator minimizes the comparator’s total delay time and enhances the sample rate. The dynamic bias architecture of the double-tail latch-type comparator can provide a relatively high voltage gain while ensuring a low power consumption by stabilizing the static operating point. It also has advantages over conventional comparators in noise and delay. A triple-latch feedforward (TLFF) comparator improves on the triple-tail fully dynamic comparator. The triple-latch feedforward (TLFF) dynamic comparator consists of three-stage latches and a parallel feedforward path. It has a smaller delay time than other circuit designs, especially for large differential input signals.