Feedforward Path Research Articles

An Improved Synchronization Stability Method of Virtual Synchronous Generators Based on Frequency Feedforward on Reactive Power Control Loop

The synchronization stability of the virtual synchronous generator (VSG) under grid fault is an important issue for maintaining stable operation in the power system. Existing work has pointed out a low-pass filter (LPF) with a sufficiently low cutoff frequency in the reactive power control loop (RPCL) can improve the transient stability. Yet, the underlying mechanism was unknown. Moreover, as a key index of VSG and precondition of synchronization stability, the frequency response is rarely studied. In this article, based on the linearized model for qualitative analysis, combined with the nonlinear model for quantitative analysis, the underlying mechanism of improving synchronization stability using an LPF in the RPCL is revealed. Furthermore, to avoid increasing the system order and solve the conflict between transient stability and frequency response, an improved synchronization stability method is proposed by feedforwarding the frequency difference between the VSG and grid to the RPCL. The frequency response is also acquired based on the combined linearized and nonlinear model, which shows that the frequency feedforward method can further enhance the frequency stability. How to design the coefficient of the frequency feedforward path with different inertia requirements is also presented. Finally, this method is verified by experimental results.

Overshoot Damping and Dynamics Improvement in Wireless Power Transfer Systems via Receiver-Side Controller Design

Buck converters have been extensively used for output regulation in the receiver of series–series compensated wireless power transfer (WPT) systems. Nonetheless, there are two major challenges in the controller design of this class of WPT systems. First, due to the current-source nature and finite dc-link capacitance, a right-half-plane (RHP) zero exists in the WPT receiver, reducing its stability margin and causing limited system dynamics. Second, this RHP zero can cause an overshoot issue in the WPT system. Without proper treatment, this overshoot may largely increase the voltage/current stress of the system and even cause catastrophic failure. However, existing solutions to the above two issues suffer from long communication delays or significantly compromised output regulation, degrading system performance. In this article, the slow dynamics and the overshoot issue of the WPT system are elaborated in theory and a solution is proposed by adding a feedforward path of the dc-link voltage in the receiver's controller. No communication is involved in the proposed control method, and only trivial computation is added to the controller. The proposed method is examined on a WPT prototype. The experimental results show that the two issues of the WPT system can be simultaneously solved by the proposed method while the output regulation of the system is not compromised.

Electronically Reconfigurable and Tunable Fractional-Order Filter Using Resonator Concept and Feedforward Path for Low-Frequency Tone Signalization

A novel electronically reconfigurable fractional-order filter allowing independent electronic frequency tuning and switchless change of the transfer response by a single parameter between standard band-pass, inverting all-pass response and special type band-reject response is presented in this work. The differences between these special transfer characteristics and standard features consist in magnitude and phase response behavior. Inverting amplification or attenuation is also available. The filter has tested frequency range between 1 Hz and 100 kHz. The proposed fractional-order filter (using two fractional-order element having equivalent capacity 8.7 uF/sec1/4, α = 3/4) tunability yields one-decade range approximately between 10 Hz and 100 Hz by transconductance between 0.19 and 1.1 mS (fractional-order design helps with reduction of driving force less than one decade). The application example in frequency/phase detector (operationability around center frequency 100 Hz - between 50 and 180 Hz) and further signaling frequency detecting system for frequency shift keying demodulator offers maximal detectable voltage (about 300 mV) for alignment (zero phase shift) of the signals of the same frequency (center frequency of the proposed filter in inverting all-pass mode). It also offers an interesting application in frequency shift keying demodulation process (or for identification/signalization purposes of certain frequencies) by usage of a simple additional comparator generating clear output state. Cadence simulations as well as experimental tests using integrated cells of special multipliers fabricated in ON Semiconductor 0.35 μm I3T25 CMOS process confirm operationability of the proposed concept as well as simple application of special response of the filter for phase/frequency detection and demodulation purposes.

Energy Efficiency in Slew-Rate Enhanced Single-Stage OTAs for Switched-Capacitor Applications

Slew-rate enhancement (SRE) techniques assist the charge transfer process in OTA-based switched-capacitor circuits. Parallel-type slew-rate enhancement circuits, i.e., circuits that provide a feed-forward path external to the main OTA, are attractive solutions, since they introduce a further degree of freedom in the speed/power consumption design space without affecting other specifications regarding the main OTA. This technique lends itself to be employed jointly with advanced OTA topologies in order to compose a highly energy efficient OTA/SRE system. However, insights in design choices such as power optimization are still missing for such systems. Here we discuss system level choices with the help of a simple model. Using precise electrical simulations, we demonstrate energy savings greater than 30% for different OTA/SRE systems implemented in a standard 180-nm CMOS technology.

A 40-MHz Bandwidth 75-dB SNDR Partial-Interleaving SAR-Assisted Noise-Shaping Pipeline ADC

This article presents a successive approximation register (SAR)-assisted noise-shaping (NS) pipeline analog-to-digital converter (ADC) incorporating various techniques to improve its bandwidth (BW), energy efficiency, and robustness. A multiple-input dynamic amplifier is used for both residue amplification and error feedback (EF) summation, thus realizing a 1st-order NS with low power consumption. An additional residue feed-forward (FF) path is introduced in the 2nd-stage SAR ADC to compensate for the noise transfer function (NTF) deterioration caused by the gain mismatch in the multiple-input pairs of the dynamic amplifier. The partial-interleaving 1st stage breaks the speed bottleneck of the conventional three-phase timing arrangement, which significantly enhances the overall ADC's speed and sampling performance. Besides, a coarse SAR ADC is introduced to further speed up the conversion with low power, while simultaneously enabling the enclosure of the data-weighted-averaging (DWA) on the DAC without a speed penalty. Finally, a low-cost inter-stage offset calibration is proposed that aligns the offset voltages among stages in the background without requiring an extra phase. Fabricated in the 28-nm CMOS process, the prototype achieves a signal-to-noise-and-distortion ratio (SNDR) of 75.2 dB over 40-MHz BW with only 7.5 over-sampling rate (OSR). Under a 1-V supply voltage, the ADC consumes 2.56 mW and exhibits a Scherier figure-of-merit (FoM) of 177.1 dB.

An Efficient Pseudo-Derivative-Feedback-Based Voltage Controller for DVR Under Distorted Grid Conditions

Grid integration of distributed energy resources has become a technical challenge in the distribution network operation due to the intermittent nature of renewable energy sources and their impact on grid voltage stability. Thus, a dynamic voltage restorer (DVR) is installed in the distribution network system to reduce such grid voltage impact on sensitive loads. In this article, a pseudo-derivative-feedback (PDF)-based voltage controller is implemented for the effective operation of DVR under voltage disturbances. Response of DVR primarily depends upon its controller action. This article addresses the issues in conventional P and PI multiloop controller with and without feedforward path then proposes PDF control strategy for DVR. Using the proposed controller, dynamic performance of DVR is improved. The efficacy of the proposed controller is illustrated by a comparative study with conventional P and PI controller using time response and relative stability analysis. Finally, PSCAD simulation studies for a 10 kV medium voltage DVR and experimental results using a low voltage laboratory prototype DVR are presented to prove the robustness of proposed controller for DVR under symmetric and asymmetric voltage sags.

Active disturbance rejection control for ship course tracking with parameters tuning

A course tracking control law is designed based on the active disturbance rejection control (ADRC) technique for ships with unknown dynamic parameters and unknown time-varying disturbance under input saturation, which consists of feed-forward compensation and an error feedback proportional-derivative (PD) control law. The compound uncertainties, due to the unknown dynamic parameters, unknown time-varying disturbance, and input saturation, are viewed as a total disturbance, which is estimated through an extended state observer (ESO) and effectively compensated in the feed-forward path. Subsequently, an extremum seeking algorithm without steady-state oscillation (ESA-SSO) is introduced to tune the design parameters of the ADRC-based ship course tracking control law so as to obtain the better performance of ship course tracking control. The strict stability analysis shows that the resulting closed-loop course tracking control system of ships is uniformly stable. Finally, simulation results and comparisons on a frigate are presented to illuminate the effectiveness and the superiority of the designed control law.

A +0.66/−0.73 °C Inaccuracy, 1.99-μW Time-Domain CMOS Temperature Sensor With Second-Order ΔΣ Modulator and On-Chip Reference Clock

This paper presents a compact and low-power time-domain CMOS temperature sensor intended for Internet of Things. To eliminate the off-chip reference clock that is commonly needed for time-domain CMOS temperature sensors, a precise on-chip reference clock is designed to measure the temperature-dependent delay generated by an inverter chain with even stages. In the reference clock circuit, a relaxation oscillator showing discharging phases with negative temperature coefficient (TC) is designed, which are compensated by 2 identical inverter-chains with positive-TC delay, resulting in a reference clock with nearly temperature-independent pulse width and period. In addition, a 2nd-order hybrid time-voltage delta-sigma (ΔΣ) modulator with feedforward path is proposed to quantize the temperature-dependent delay of the main inverter chain, achieving 100-mK resolution only in about 25-ms conversion time. Fabricated in 0.18-μm CMOS, measurement results show that the best (worst)-case temperature accuracy of the clock's reference time is ±0.015% (±0.055%) and the temperature sensor achieves a maximum inaccuracy of +0.66/-0.73°C from -20°C to 80°C. The prototype occupies 0.45-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip area and consumes 1.99-μW from a 1.8-V supply at room temperature.

A 5.6 μ A Wide Bandwidth, High Power Supply Rejection Linear Low-Dropout Regulator With 68 dB of PSR Up To 2 MHz

High power supply rejection (PSR) with a wide rejection frequency band is becoming a critical requirement in linear low-dropout regulators (LDOs) used in complex systems-on-chip (SOCs). Typical LDOs achieve higher PSR within their loop-bandwidth; however, their supply rejection performance degrades with reduced loop-gain outside their loop-bandwidth. Typical LDOs with external filtering capacitors may also have spectral peaking in their PSR response, causing excess system-level supply noise. This work presents an LDO design approach, which achieves a PSR of higher than 68 dB up to 2 MHz frequency and over a wide range of loads up to 250 mA. The wide PSR bandwidth is achieved using a current-mode feedforward ripple canceller (CFFRC) amplifier which provides up to 25 dB of PSR improvement. The feedforward path gain is inherently matched to the forward gain of the LDO, not requiring calibration. The LDO has a fast load transient response with a recovery time of 6.1 $\mu \text {s}$ and has a quiescent current of 5.6 $\mu \text {A}$ . For a full load transition, the LDO achieves settling with overshoot and undershoot voltages below 27.6 and 36.36 mV, respectively. The LDO is designed and fabricated in a 180 nm bipolar/CMOS/DMOS (BCD) technology. The CFFRC amplifier helps to achieve low quiescent power due to its inherent current mode nature, eliminating the need for supply ripple summing amplifiers and adaptive biasing.

An opamp-free second-order noise-shaping SAR ADC with 4$$\times$$ passive gain using capacitive charge pump

This paper presents a compact and robust opamp-free noise shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC). The proposed NS SAR ADC adopts extra one passive feed-forward path summing in realizing second-order noise shaping with the minimum modification to a standard SAR. Compared with previous works, the noise sources of residue sampling and first-order integration on filter capacitors are obviated. It implements 4 $$\times$$ passive gain by capacitive charge-pump techniques that compensates the partial loss of residue voltage and relaxes the specifications of comparator. According to the behavioral modeling and simulation results, an ENOB of 16.88-bit is achieved based on a 10-bit DAC array, at the OSR of 16. Through utilizing the Monte Carlo simulation, the proposed ADC architecture is proven to be a robust system.

A Class-D FVF LDO With Multi-Level PWM Gate Control, 280-ns Settling Time, and No Overshoot/Undershoot

A novel class-D flipped voltage follower (FVF) low-dropout (LDO) regulator is proposed and implemented in this paper to supply high load current with fast transient response for sharp load changes. The proposed class-D control generates a multi-level pulse width modulated (MLPWM) signal to the gate of the control transistor that corresponds to the load level. The MLPWM control signal enables wide loop bandwidth and reduces output ripple. The FVF architecture reduces the output impedance and improves the controller efficiency. A novel feed-forward transition-detection path (FFTDP) controls the gate of the power transistor and allows enhanced switching at high loads. The proposed LDO operates with a wide range of input voltages from 1.2V to 1.8V and dropout of 200mV down to 50mV. The implementation responds to load changes from 0-300mA in 7ns with no observed overshoot/undershoot. The output ripple for the LDO is $_{\mathbf {V}}=1$ mV with a current efficiency of 99.93% at maximum load current. The prototype chip is fabricated on 28-nm CMOS technology and the controller occupies 0.004mm2.

An all-optical proteretic switch using semiconductor ring lasers

Proteresis, a complementary effect to well-known hysteresis, is an interesting phenomenon to be explored. As we know, the hysteretic device is a bistable switch whose states depend on the system’s history whereas the proteretic device’s states depend on the future. Though an all-optical implementation of the hysteretic device has been demonstrated but its complementary behavior has yet to be contrived. Therefore, this work presents the design and development of an all-optical proteretic system using semiconductor ring lasers. The design was achieved by providing a constraint feedforward path to a hysteretic feedback system. Additionally, the role of various parameters was studied in order to achieve proteresis. It is observed that the proteretic effect can be achieved only for specific conditions otherwise the system behaves as a traditional hysteretic device. The experimental results match well with the theoretical Simulink results.

Handling-Qualities Perspective on Rotorcraft Load Alleviation Control

The objective of this research effort is to assess the impact of load alleviation control on the quantitative handling-qualities specifications (also known as predicted handling qualities) of both conventional helicopters and compound rotorcraft in forward flight. First, an overview on how the harmonic decomposition methodology is used toward load alleviation control is presented. Next, flight control laws are developed based on an explicit model-following architecture. Parametric studies are performed to provide insights on how both the feedforward and feedback paths of the model-following control laws can be used to alleviate the rotor loads. The impact of load alleviation on predicted handling qualities is studied. It is shown that, for the standard helicopter configuration considered, load alleviation comes at the cost of a degradation in handling qualities. However, for the compound rotorcraft considered, allocation of the control signal to the redundant control surfaces provides load alleviation without degradation in predicted handling qualities. The flight control laws are subsequently optimized using the Control Designer’s Unified Interface to meet a comprehensive set of stability, handling-qualities, and performance specifications for specific mission task elements while minimizing the unsteady rotor loads.

A mismatch compensated readout IC for an uncooled microbolometer infrared FPA

In this paper, a low offset readout IC for an uncooled microbolometer infrared focal plane array is presented. It is shown that, due to the mismatch, the self-heating component of the IR-sensitive sensor’s current cannot be completely cancelled in the conventional differential structures. Therefore, there is large offset current which can desensitized the readout. The proposed readout is capable of achieving low-offset performance with using a feedforward path. A readout has been designed in a standard 0.18 μm CMOS technology. The post-layout simulation results show the feedforward path can attenuate the equivalent input offset current by about 14 dB at the presence of the 20% mismatch non-uniformity in the pixels. The noise equivalent temperature difference (NETD) is 48.5 mK which is increased by about 2.5 dB. Therefore, the overall dynamic range is increased 11.5 dB in the proposed readout. The readout draws 106.36 mA from a 3.3 V supply in a FPA with 352 × 288 pixels.

Phase-domain ADC with ∆-modulation frequency tracking loop

The principle of ∆-modulation has been leveraged in time-domain to cancel the nonlinearity of voltage to frequency transfer function in VCO-based ADCs. The proposed modulation technique features frequency-tracking loop (FTL) to compensate for the imperfection of frequency nonlinearities and to eliminate the analog Op-Amp. Injection locking is used to alleviate the mismatch effect between the feedforward and feedback paths. The circuit level design and simulation results validate the functionality. The proposed solution can achieve higher noise shaping orders and better resolutions without compromising the hardware complexity by using fully synthesizable digital accumulators.

A High‐linearity Input‐Buffer with high output common‐mode stability for 10bit 3.2GSs ADC

A high-linearity input-buffer with high output common-mode stability for 10-bit 3.2 GS/s ADC is proposed in this Letter. The buffer is mainly composed of a source follower for strong driving ability. To enhance its linearity, a feed forward signal path from input to output is proposed. A replica buffer-based common-mode feedback is designed to achieve high output common-mode stabilisation of input-buffer. The prototype is implemented in 40 nm CMOS process. The output common-mode variation is reduced from 200 to 1 mV. Input-buffer consumes 96 mW in 3.2 GHz sampling rate and achieves 69.3 dB spur-free dynamic range at 1581 MHz input frequency.

Linearity-Enhanced Ring Amplifier Using Adaptive Slew-Rate Feed-Forward Path

This brief presents a novel adaptive slew-rate ring amplifier. The proposed technique enhances the linearity, without stability degradation, using a rail-to-rail controlled feed-forward path used in parallel with the main ring amplifier. It offers additional degrees of freedom to improve the linearity/power consumption trade-off proposed in other reported slew-rate enhancement techniques. The proposed design has been implemented and simulated in a low-cost CMOS 65 nm technology. Operating from a single 0.9 V power supply, it consumes 186μA for switching frequency of 210MHz. For the same current consumption, it achieves an improvement of 10 dB in the total harmonic distortion (THD) compared to state-of-the-art.

Software-Based Self-Test Techniques for Dual-Issue Embedded Processors

Nowadays, Self-Test strategies for testing embedded processors are increasingly diffused, especially for safety critical systems. Test programs can be effectively used for this purpose. This paper describes a set of systematic self-test techniques for in-order dual-issue embedded processors. The paper shows how to produce test programs suitable for the detection of faults in five classes of sub-modules: duplicated computational modules; multi-port register file; duplicated pipeline registers and feed-forward paths; pipeline interlocking logic; and pre-fetch buffer. While some techniques extend single-issue test programs, new techniques are also shown; results are illustrated for a couple of 32-bit in-order dual-issue processors included in automotive Systems-on-Chip manufactured by STMicroelectronics.

Sparse identification of contrast gain control in the fruit fly photoreceptor and amacrine cell layer

The fruit fly’s natural visual environment is often characterized by light intensities ranging across several orders of magnitude and by rapidly varying contrast across space and time. Fruit fly photoreceptors robustly transduce and, in conjunction with amacrine cells, process visual scenes and provide the resulting signal to downstream targets. Here, we model the first step of visual processing in the photoreceptor-amacrine cell layer. We propose a novel divisive normalization processor (DNP) for modeling the computation taking place in the photoreceptor-amacrine cell layer. The DNP explicitly models the photoreceptor feedforward and temporal feedback processing paths and the spatio-temporal feedback path of the amacrine cells. We then formally characterize the contrast gain control of the DNP and provide sparse identification algorithms that can efficiently identify each the feedforward and feedback DNP components. The algorithms presented here are the first demonstration of tractable and robust identification of the components of a divisive normalization processor. The sparse identification algorithms can be readily employed in experimental settings, and their effectiveness is demonstrated with several examples.

Multi resonant Component-Based Grid-Voltage-Weighted Feedforward Scheme for Grid-Connected Inverter to Suppress the Injected Grid Current Harmonics Under Weak Grid

The grid voltage full feedforward scheme is an effective method to improve the injected grid current quality of the grid-connected inverter. However, due to the digital control delay, the suppression of the injected grid current harmonics is weakened, and the inverter output impedance has an additional negative phase shift, which deteriorates the system stability under weak grid. In this article, a multi resonant component-based grid-voltage-weighted feedforward scheme is proposed, which introduces a series of quasi-resonant components into the grid voltage full feedforward path so that only the background harmonics in the grid voltage are fed forward. By properly designing the quasi-resonant components, the phase lag due to the digital control delay is compensated and the feedforward weights at different harmonic frequencies are introduced in the grid voltage feedforward path. Thus, the suppression of the injected grid current harmonics and the system stability is improved. The experimental results from a 6-kVA prototype are provided to verify the effectiveness of the proposed grid-voltage-weighted feedforward scheme.