Feedforward Path Research Articles

Low-voltage high-gain large-capacitive-load amplifiers in 90-nm CMOS technology

Low-voltage and low-power multistage operational transconductance amplifiers with new and efficient gain boosting and frequency compensation schemes are proposed in this paper. The presented amplifiers are designed to drive large capacitive loads with small power consumption at low-voltage supplies. The compensation schemes exploit a single Miller capacitor and an active feedback to form the main negative feedback loops for pole splitting and two feedforward paths. The new gain boosting technique discussed here improves the dc gain with negligible effect on the frequency response. The analysis and design procedures are discussed and the performance enhancements of the amplifiers are verified. The proposed OTAs have been implemented in a standard 90-nm CMOS process and the post-layout simulation results are reported. The amplifiers consume 8.7μW and 8.1μW at 0.5-V supplies and achieve 12.65MHz and 2MHz gain-bandwidth products while driving 150-pF and 15-nF capacitive loads, respectively.

Robust to PVT enhanced DC gain amplifier using no Miller capacitor feedforward compensation

This paper presents an operational transconductance amplifier compensated in frequency with a feedforward path implemented with current mirrors. This concept eliminates the need of Miller capacitor and improves performance compared to traditional feedforward topologies in regard to DC gain. Gain enhancement is achieved because of the use of current mirrors which reduces the number of the conductances that are connected to the output and increasing output impedance. Moreover, common mode range is improved by the PMOS differential pair used in the feedforward stage. Simulations results for the designed circuit on the typical UMC 180 nm CMOS process, show a DC gain above 60 dB with a unity gain frequency of 511 MHz, a phase margin (PM) of 49 $$^{\circ }$$ � , a slew rate (SR) of 205�V/ $${\upmu }$$ μ s and a power consumption of 5.1 mW maintaining low variations in regard to process, voltage and temperature variations.

A 1.2 V 600 nW 12-bit 2 kS/s incremental ADC for biosensor application

This paper presents an ultra-low power incremental ADC for biosensor interface circuits. The ADC consists of a resettable second-order delta—sigma (Δ Σ) modulator core and a resettable decimation filter. Several techniques are adopted to minimize its power consumption. A feedforward path is introduced to the modulator core to relax the signal swing and linearity requirement of the integrators. A correlated-double-sampling (CDS) technique is applied to reject the offset and 1/f noise, thereby removing the integrator leakage and relaxing the gain requirement of the OTA. A simple double-tailed inverter-based fully differential OTA using a thick-oxide CMOS is proposed to operate in the subthreshold region to fulfill both an ultra-low power and a large output swing at 1.2 V supply. The signal addition before the comparator in the feedforward architecture is performed in the current domain instead of the voltage domain to minimize the capacitive load to the integrators. The capacitors used in this design are of customized metal—oxide—metal (MOM) type to reach the minimum capacitance set by the kT/C noise limit. Fabricated with a 1P6M 0.18 μm CMOS technology, the presented incremental ADC consumes 600 nW at 2 kS/s from a 1.2 V supply, and achieves 68.3 dB signal to noise and distortion ratio (SNDR) at the Nyquist frequency and an FOM of 0.14 pJ/conversion step. The core area is 100 × 120 μm2.

저전력 동작을 위한 지연된 피드-포워드 경로를 갖는 3차 시그마-델타 변조기

본 논문은 전력소모와 면적을 줄인 지연된 피드-포워드 경로를 갖는 3차 SDM 구조를 제안하였다. 제안한 SDM은 기존의 적분기 2개로 구현된 3차 SDM(Sigma-Delta Modulator) 구조를 개선하였다. 제안된 구조에서는 기존 구조의 둘째 단에 지연된 피드-포워드 경로를 삽입함으로써 첫째 단의 계수 값을 2배로 증가시킬 수 있어 기존구조에 비하여 첫째 단 적분기 커패시터(CI)를 1/2로 감소시킬 수 있다. 그러므로 첫째 단 적분기의 부하 커패시턴스가 1/2로 작아지기 때문에 첫째 단 연산증폭기의 출력전류는 51%, 첫째 단의 커패시터 면적은 48% 감소되어 제안한 구조는 전력과 면적을 최적화 할 수 있다. 본 논문에서 제안한 구조를 이용하여 설계된 3차 SC SDM은 0.18μm CMOS 공정에서 공급전압 1.8V, 입력신호 1Vpp/1KHz, 신호대역폭 24KHz, 샘플링 주파수 2.8224MHz 조건으로 시뮬레이션 하였다. 그 결과 SNR(Signal to Noise Ratio) 88.9dB, ENOB(Effective Number of Bits) 14비트이고 SDM의 전체 전력소모는 180μW이다.

Feedforward Control Design Based on Laguerre Network Modelling

In this paper feedforward control algorithm is proposed to enhance the performances of the model reference control. The control design is based on discrete Laguerre networks which represent a simple and useful tool for the approximation of signals or systems. In this approach both the system model and the controller are expressed in the form of Laguerre network. The model reference control is an open-loop control strategy which aims at obtaining an optimal reference signal tracking. To ensure unmeasured disturbance rejection the control loop is closed using an additional integrating effect. A feedforward path is added to reject the effect of measurable disturbance with known dynamics.

A fast-transient high-PSR output-capacitor-free low-dropout regulator for low-power embedded systems

A low-power fast-transient output-capacitor-free low-dropout regulator (LDO) with high power-supply rejection (PSR) is presented in this paper. The proposed LDO utilizes a non-symmetrical class-AB amplifier as the input stage to improve the transient performances. Meanwhile, PSR enhancement circuit, which only consumes 0.2-µA quiescent current at light load, is utilized to form a feedforward cancellation path for improving PSR over wide frequency range. The LDO has been designed and simulated in a mixed signal 0.13-µm CMOS process. From the post simulation results, the LDO is capable of delivering 100-mA output current at 0.2-V dropout voltage, with 3.8-µA quiescent current at light load. The undershoot, the overshoot and the 1 % settling time of the proposed LDO with load current switching from 50 µA to 100 mA in 300 ns are about 100 mV, 100 mV and 1 µs, respectively. With the help of proposed PSR enhancement technique, the LDO achieves a PSR of ?69 dB at 100 kHz frequency for a 100-mA load current.

A state-space approach for control of NPC type 3-level sine wave inverter used in FOC PMSM drive

Abstract This paper presents the design and analysis process of state feedback controllers for NPC type 3-level sine wave inverter. In order to achieve good dynamic features in a state feedback control an internal model of reference input and a feedforward path are introduced. During synthesis process of the state feedback controllers maximum permissible dynamics of voltage control in the linear range of modulation is taken into account. It is shown that initially gains of the controller and feedforward path are non-stationary and depend on the angular velocity. Stationary approximation of a non-stationary state feedback controller is presented in details. Proposed state feedback control structures for continuous voltage shaping NPC type 3-level voltage source inverter are examined in FOC PMSM drive. The novelty of the presented controller lays in a stationary approximated state feedback control structure designed in terms of maximum permissible dynamics of a voltage control system. Simulation and experimental results (at the level of 3 kW) of the designed control algorithms are included.

DCCII based frequency compensation method for three stage amplifiers

A new frequency compensation scheme using a second generation differential current conveyor (DCCII) for three-stage amplifiers is proposed. By adding a DCCII as a feedback path from output of the second and the third stage to the output of the first stage, feed-forward path and the right-half plane zero will be removed subsequently, which significantly improves phase margin and gain-bandwidth product. Calculations are derived for two states. First state, a DCCII and two miller capacitors form the feedback paths and in the second state, two nulling resistors will be set series with miller capacitors. Analyses show that in both states, stability can be perfectly ensured.To demonstrate advantages of this technique over the traditional RNMC architecture, a three-stage amplifier is designed and simulated employing the proposed technique in a standard 0.18μm CMOS process. Simulation results show that, with the same load capacitance, the new amplifier achieved 85° and 9.63MHz as phase margin and gain-bandwidth product, respectively. The proposed amplifier dissipates only 0.31mW of power with a 1.8V supply.

Identification and cuckoo PI-PD controller design for stable and unstable processes

In this paper, a method for the identification and control of stable and unstable processes is proposed. Firstly, a second-order plus delay time process model is identified using an ideal relay in the feedforward path and then, a proportional integral–proportional derivative (PI-PD) controller is designed based on the identified process model. The PD controller is designed that stabilizes the process and the PI controller is designed using the cuckoo optimization algorithm. The effectiveness of the proposed identification and control method is illustrated and verified by simulation and experimental results.

Boundary Conduction Mode Controlled Power Factor Corrector With Line Voltage Recovery and Total Harmonic Distortion Improvement Techniques

The proposed line voltage recovery (LVR) and the total harmonic distortion improvement (THDI) technique improve power factor (PF) and total harmonic distortion (THD) over a wide line voltage range in boundary conduction mode controlled power factor corrector (PFC). The LVR detects the input line root-mean-square voltage to generate the digital equivalent code to the THDI for optimizing the THD by tuning the on-time value at different line voltages. In addition, the LVR and the THDI provide a feedforward path to reduce the ripple of the feedback voltage for further improving the THD. Therefore, the PFC controller can keep high PF and low THD over a wide line voltage. Experimental results demonstrate that the peak PF value is 0.998 and the minimum THD is 1.7% by the test circuit fabricated in a TSMC 800-V ultrahigh-voltage process with the universal line voltage range of 90-264 V.

Soliton generation from a fundamentally mode-locked fiber laser with a feed-forward path

We demonstrate for the first time to our knowledge, the soliton generation from a mode-locked erbium-doped fiber laser using a novel saturable absorber (SA), which is realized by combining a dual-drive modulator and an intensity feed-forward path. The laser is fundamentally mode-locked under high-frequency RF signal modulation. Experimentally, the actively mode-locked laser produces a 16.7 MHz repetition rate pulse train with a 1.4 ps pulse width, and the spectrum bandwidth is 2.17 nm. The results demonstrate that the SA supports soliton pulse shaping in the cavity at the fundamental frequency.

An Improved Path Tracking Algorithm for Intelligent Vehicle in Automatic Parking Conditions

A feedforward and feedback path tracking algorithm appropriate for automatic parking is proposed in this paper. This algorithm is composed of feedforward control and feedback control. In the path tracking, vehicle position and reference path information are used to calculate the lateral and heading error of the vehicle as well as the curvature of reference path, and put these three as the system inputs, the steering angel of the vehicle as the output. The system parameters are settled by multiple tests. Experiments show that, this method has a high performance in path tracking and meets the requirements of vehicle parking in both low speed situation and narrow spaces.

A wide-bandwidth PSR-enhanced low-dropout regulator using a bandpass feedforward supply ripple rejection circuit

A low-dropout regulator with a wide-bandwidth feedforward supply noise cancellation path for enhancing supply noise rejection at middle-to-high frequency is presented in this paper. This idea has been realized by a bandpass filter and a signal-nulling technique with the help of a voltage buffer. For the PSR filter design, the total on-chip capacitance is about 18.75 pF. This circuit has been implemented in a 0.35 µm CMOS process and occupies an active chip area of 0.062 mm2. From the experimental results, the proposed LDO can operate with nominal dropout voltage of 200 mV at maximum load of 25 mA and quiescent current of 26 μA. It achieves a power-supply rejection better than ?59 dB up to 10 MHz with a 4 μF output capacitor.

High-performance tracking of high-speed supercavitating vehicles with uncertain parameters using novel parameter-optimal iterative learning control

SUMMARYThis paper proposes a new technique based on a Parameter-Optimal Iterative Learning Control (POILC) to track a command pitch rate of a high-speed supercavitating vehicle (HSSV). The pitch rate of a supercavitating vehicle has non-minimum phase behavior. Thus, tracking is fundamentally limited to poor performance. To solve this problem, a feed-forward control can be used while using the cavitator as a control input in the feed-forward path to modify the slow response caused by non-minimum phase behavior. The main idea of this paper is to apply the cavitator input with high precision as a feed-forward control to improve tracking performance. The exact value of the feed-forward control is achieved using POILC. However, in the presence of uncertainty, zero convergence of POILC algorithms is threatened. It will be shown that applying adaptive weight in the performance index, the convergence is guaranteed in the presence of uncertainty and also when the system is sign-indefinite. The proposed technique includes an optimal planning to make the error norm monotonically convergent to zero. The convergence and perfect tracking will be guaranteed through a Lyapunov candidate. Performance and significance of the proposed supercavitating vehicle control will be verified by simulation.

A 16-bit sigma–delta modulator applied in micro-machined inertial sensors

A fourth-order low-distortion low-pass sigma–delta (ΣΔ) modulator is presented for micro-machined inertial sensors. The proposed single-loop single-bit feedback modulator is optimized with a feed-forward path to decrease the nonlinearities and power consumption. The IC is implemented in a standard 0.6 μm CMOS technology and operates at a sampling frequency of 3.846 MHz. The chip area is 2.12 mm2 with 23 pads. The experimental results indicate a signal-to-noise ratio (SNR) of 100 dB and dynamic range (DR) of 103 dB at an oversampling rate (OSR) of 128 with the input signal amplitude of −3.88 dBFS at 9.8 kHz; the power consumption is 15 mW at a 5 V supply.

A process-tolerant out-of-band blocker rejection technique for SAW-less receivers

In this paper, an active filtering technique is presented which is capable of filtering the out-of-band blockers in wireless receivers. The concept is based on the feedforward cancellation technique where a blocker replica is subtracted at the output of the low-noise amplifier (LNA). In contrast to the previously reported feedforward cancellation methods, exact gain and phase matching are easily obtained in the proposed architecture to produce a highly selective narrowband frequency response at the output of the LNA with wide rejection bandwidth. For the proof of concept, the system is implemented in a 65nm CMOS technology. It occupies a total area of 0.8mm2 and the current consumption is 24mA from a 1.2V supply. The system post-layout simulations showed a blocker rejection of more than 33dB for blocker signals 100MHz away from the desired signal when the feedforward path is activated. The noise figure (NF) of the entire system is 3.8dB that degrades to 5.8dB when the feedforward path is activated.

Improved Optimal Controller Designs for All Pole Systems and Standard Forms with One/Two Variable Zeroes

Use of the standard forms for controller design is known for a long time. Since first introduced in 1950s, many new contributions have been proposed in the literature. In these contributions, the standard forms are obtained for all poles and with no zero, one zero and two zeroes systems. In this study, for the first time, optimum values of standard form coefficients with two variable zeroes are obtained using only one constrained for the Integral Squared Time Error (ISTE) and Integral of the Squared Time Error (IST2E) criteria. Again in this study, an improved generalized controller design approaches using standard forms with all pole and two variable zeroes have been given for nth degree all pole systems. By improving the previously proposed approaches, stabilities of the overall transfer functions have been guaranteed. In the proposed approaches, a PI or PID controller in the feed forward path and a polynomial controller, which its degree changes according to system degree in the inner feedback path, have been used. Parameters of these controllers are obtained using the standard form coefficients and the proposed simple mathematical operations without the restrictions of the previously proposed approaches. Comparative examples for the use of the proposed approaches and the obtained standard forms together with the previously proposed methods are also given in the MATLAB. DOI: http://dx.doi.org/10.5755/j01.eee.20.2.4135

Process-Variation-Calibrated Multiphase Delay Locked Loop With a Loop-Embedded Duty Cycle Corrector

A multiphase delay locked loop (DLL) that can calibrate the interphase error and guarantee the 50% duty cycle of the output clock of the DLL is presented. The proposed process variation calibration architecture is implemented without the need for complex circuitry because it calibrates the phase error using a simple delay averaging operation among four 90° shifters. In addition, a loop-embedded duty cycle corrector is implemented with extremely small power and area requirements by adopting feedforward and feedback paths. Finally, a sense-amplifier-based phase detector is proposed for reducing dithering jitter. The proposed DLL is fabricated using a 0.13- μm CMOS process. For the seven test chips analyzed, the proposed DLL had a maximum phase error of 1.8° and a duty cycle error of 0.97% at 800 MHz.

Inverse compensation for hysteresis in piezoelectric actuator using an asymmetric rate-dependent model

This paper presents a modified Bouc-Wen model for asymmetric rate-dependent hysteresis in piezoelectric actuator. On this basis, we develop a new digital inverse controller with a simple structure cascaded in the feedforward path for piezoelectric actuator. In order to eliminate modeling errors and parameter uncertainties, the developed inverse controller is combined with a feedback loop to establish a hybrid control scheme. In our experiments, the proposed model together with the developed hybrid control scheme has shown significantly reduced tracking errors caused by asymmetric rate-dependent hysteresis in piezoelectric actuator.

A Digital Golay-MPIC Time Domain Equalizer for SC/OFDM Dual-Modes at 60 GHz Band

In this paper, a digital time domain equalizer (TDE) for 60 GHz radio frequency transmission systems is presented. Significantly, the TDE supports both single carrier (SC) and orthogonal frequency-division multiplexing (OFDM) operation modes for digital baseband receiver. In order to improve the performance, the proposed TDE adopts Golay sequence aided one-shot channel estimation and modified multi-path interference cancellation (MPIC) equalization. Targeting on the line-of-sight (LOS) channel characteristic, MPIC is simplified with single-tap for complexity reduction. From the area efficiency point of view, both SC and OFDM modes are designed within a single hardware to yield 99% of area sharing. The Golay-MPIC TDE structure is realized as feed-forward data path with 8X-parallelism to achieve 2.64 GS/s at 330 MHz clock rate. The Golay-MPIC TDE is fabricated as a part of a digital baseband with 65 nm 1P9M general purpose process. The area of Golay-MPIC TDE occupies 1.05 mm2 with 405 K gate counts. Besides, the power dissipations for SC and ODFM modes are 56.71 mW@220 MHz (1 V) and 91.29 mW@330 MHz (1.1 V), respectively. Finally, the chip can provide the maximum throughput 15.84 Gb/s (2.64 GS/s with 64-QAM modulation).