Energy Efficiency in Slew-Rate Enhanced Single-Stage OTAs for Switched-Capacitor Applications

Alessandro Catania,Massimo Piotto,Paolo Bruschi,Michele Dei,Mattia Cicalini

doi:10.3390/jlpea11010001

Alessandro Catania, Massimo Piotto + Show 3 more

Open Access

https://doi.org/10.3390/jlpea11010001

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Abstract

Slew-rate enhancement (SRE) techniques assist the charge transfer process in OTA-based switched-capacitor circuits. Parallel-type slew-rate enhancement circuits, i.e., circuits that provide a feed-forward path external to the main OTA, are attractive solutions, since they introduce a further degree of freedom in the speed/power consumption design space without affecting other specifications regarding the main OTA. This technique lends itself to be employed jointly with advanced OTA topologies in order to compose a highly energy efficient OTA/SRE system. However, insights in design choices such as power optimization are still missing for such systems. Here we discuss system level choices with the help of a simple model. Using precise electrical simulations, we demonstrate energy savings greater than 30% for different OTA/SRE systems implemented in a standard 180-nm CMOS technology.

Highlights

The settling behaviour of Switched-Capacitor (SC) stages, as the one depicted in Figure 1a, has been conveniently described by a simplified model [1,2,3,4,5,6,7,8]. This model breaks down the charge-transfer operation in a SC stage, whether a SC amplifier or a SC integrator, into two phases, corresponding to the idealized operating regions of the OTA: slew rate and linear regions
The remainder of this paper is organized as follows: Section 2 develops the settling-time model for power-aware system-level choices; Section 3 introduces energy metrics to evaluate the performances of different OTA/Slew-rate enhancement (SRE) systems by the means of accurate electrical simulations; Section 4 concludes this work by stating the major findings
The Itail estimation is quite accurate for FC1 and FC2, while the evident underestimation for RFC1 and RFC2 can be ascribed to the simplistic modeling

Summary

Introduction

The settling behaviour of Switched-Capacitor (SC) stages, as the one depicted in Figure 1a, has been conveniently described by a simplified model [1,2,3,4,5,6,7,8]. We are interested in the case of large voltage steps which trigger the OTA to operate initially in its slewing region This leads us to point out that both t1 and t2 depends on ∆VS respectively through ∆Vi (0+ ) and Vine. For this OTA, a simple linear relationship between its Gm (weak inversion operation of input devices) and Iomax exists, which can be shown to be: τ Iomax = 2nUT CS0. The remainder of this paper is organized as follows: Section 2 develops the settling-time model for power-aware system-level choices; Section 3 introduces energy metrics to evaluate the performances of different OTA/SRE systems by the means of accurate electrical simulations; Section 4 concludes this work by stating the major findings

System-Level Settling Model

Model Extension to Advanced OTA Topologies

Findings

Conclusions