A 40-MHz Bandwidth 75-dB SNDR Partial-Interleaving SAR-Assisted Noise-Shaping Pipeline ADC

Abstract

This article presents a successive approximation register (SAR)-assisted noise-shaping (NS) pipeline analog-to-digital converter (ADC) incorporating various techniques to improve its bandwidth (BW), energy efficiency, and robustness. A multiple-input dynamic amplifier is used for both residue amplification and error feedback (EF) summation, thus realizing a 1st-order NS with low power consumption. An additional residue feed-forward (FF) path is introduced in the 2nd-stage SAR ADC to compensate for the noise transfer function (NTF) deterioration caused by the gain mismatch in the multiple-input pairs of the dynamic amplifier. The partial-interleaving 1st stage breaks the speed bottleneck of the conventional three-phase timing arrangement, which significantly enhances the overall ADC's speed and sampling performance. Besides, a coarse SAR ADC is introduced to further speed up the conversion with low power, while simultaneously enabling the enclosure of the data-weighted-averaging (DWA) on the DAC without a speed penalty. Finally, a low-cost inter-stage offset calibration is proposed that aligns the offset voltages among stages in the background without requiring an extra phase. Fabricated in the 28-nm CMOS process, the prototype achieves a signal-to-noise-and-distortion ratio (SNDR) of 75.2 dB over 40-MHz BW with only 7.5 over-sampling rate (OSR). Under a 1-V supply voltage, the ADC consumes 2.56 mW and exhibits a Scherier figure-of-merit (FoM) of 177.1 dB.