Low Frequency Current Ripple Suppression for Two-Stage Single-Phase Inverter Based on Impedance Editing

Abstract

The instantaneous output power of the two-stage single-phase inverter pulsates at double-line frequency, generating a large amount of second harmonic current (SHC) in the front-end dc-dc converter and input dc source. The SHC is harmful to the system performance. To address the issue, a control strategy based on port-impedance editing, where inductor current feedforward (ICFF) and bus voltage feedforward paths are employed, is proposed to reduce the low frequency ripple in the article. Due to only bandpass filter employed in each feedforward path, the proposed control scheme is relatively easy to be implemented. Under the control strategy, the dc-bus port-impedance of dc-dc converter is increased rapidly at double-line frequency, while staying low impedance for other frequencies. What is more, different ICFF paths are taken into insight to obtain optimized path. Meanwhile, the small signal model of front-end dc-dc converter is established and the design principle of key parameters is provided for the derived control strategy. Furthermore, the dynamic response with bandwidth limitation is also discussed in this article. Finally, a two-stage single-phase inverter prototype was fabricated and tested. The experimental results verify the performance of the proposed strategy with SHC reduction.