Research on Four Different Designs of Comparator

Abstract

Abstract Comparators contribute a significant role to analogue to digital converters (ADC). This paper describes and evaluates four excellent comparator optimisation schemes in recent years and analyses their advantages and disadvantages, providing ideas for the following comparator research direction. In addition, this paper introduces the design steps of each comparator optimisation scheme. It shows how the designer completes the final optimisation scheme step by step from the practical problems, which provides a specific reference for the comparator designers in the future. A double-tail latch-type comparator with dynamic bias adds a tail capacitor to the pre-amplifier to achieve low noise and high gain. Furthermore, a triple-tail dynamic comparator addresses a cascoded integrator. The new stage defines and attenuates the noise to achieve high speed and low noise. Compared to the triple-tail comparator, another design of a three-stage comparator is through adding a feedforward path between the first amplifier/latch and third latch to construct a triple-latch feedforward dynamic comparator. It is aimed to reduce delay and get low consumption in the region of the high voltage signal. Moreover, Edge-Pursuit Comparator (EPC) uses NAND gates and inverter delay cells to generate the comparison result between two input signals. Its circuit structure allows input noise tunability, automatic energy scaling, and low voltage tolerance.