An 80μV<inf>rms</inf>-temporal-noise 82dB-dynamic-range CMOS Image Sensor with a 13-to-19b variable-resolution column-parallel folding-integration/cyclic ADC

Abstract

Low-noise CMOS image sensors (CIS) employing column-parallel amplifiers that significantly reduce temporal noise, as well as electron-multiplication CCD (EM-CCD) image sensors are becoming popular for very-low-light-level imaging. These low-noise imagers with high-gain amplification in either the charge or voltage domains sacrifice the intra-scene dynamic range. Scientific applications of solid-state imagers strongly require very low temporal noise and wide intra-scene dynamic range as well as very high gray-scale resolution. A column-parallel analog-to-digital converter (ADC) and column-level signal processing in CISs are key techniques to meet these requirements. Single-slope [1,2], successive-approximation [3] and cyclic ADCs [4] are widely used for the column-parallel ADC in CMOS imagers. However, these ADCs require additional gain enhancements to achieve very low temporal noise. A recently reported [5] delta-sigma (ΔΣ) ADC has an attractive feature that low temporal noise and high resolution can be simultaneously attained by an oversampling technique. However, for very high resolution, a high number of samplings per pixel output, e.g., more than 360 samplings for 16b, is required.