Low Power High Gain Fully Integrated CMOS Power Amplifier using Power Combining and Mode Locking Architecture

Abstract

The power amplifier (PA) is one of the building blocks of a transmitter, which operates directly on the antenna. The PA’s low power radio frequency (RF) input signal is amplified into a significant power RF output signal by converting DC power to RF power. Performance is one of the most important roles in the design of the PA because it utilizes most of the PA. Performance is one of the most important metrics in the design of power amplifiers. Conventional designs provide maximum performance at a single power level, usually near the maximum rated power of the amplifier. In this paper, we propose a low power high gain fully integrated CMOS power amplifier (LPHG-PA) using power coupling and mode locking configuration. Low power consumption is achieved with high voltage and power gain, while high gain utilizes a fully integrated configuration. In this configuration, we have a good tradeoff between low noise, high gain and sustainability. Using the common-gate (CG) configuration, we minimized the parasitic effects of CGD, resulting in the stability and linearity of the amplifier. This configuration also provides reverse isolation, which is important in LNA design. Finally, the proposed LPHG-PA can be implemented in Cadence tool with CMOS 180nm technology. The efficiency of the proposed design is compared with the existing sophisticated power amplifiers.