Design of a high gain and low noise CMOS folded mixer for 5GHz with low power consumption

Abstract

In this paper, a high gain and low noise down-conversion mixer based on TSMC 0.18 µm CMOS technology for 5 GHz wireless applications is presented. To facilitate low power operation, the proposed mixer adopts folded double balanced Gilbert topology with PMOS for LO switching stage. The self-bias resistive current reuse configuration is employed in the RF transconductance stage to achieve high conversion gain (CG). Since the folded topology allows RF stage and LO stage to be biased independently, current bleeding technique has been utilized to further improve the conversion gain, noise figure and linearity. The simulation results demonstrate that the proposed mixer can provide 17.9 dB of conversion gain with a local oscillator power of −4 dBm, a noise figure (NF) of 9 dB, while the power consumption is only 0.9mW under 1V supply voltage, and the input-referred third-order intercept point of this mixer is −1.4 dBm. Comparing with the previously reported CMOS mixers, the proposed work has the advantages in the performance of high gain, low noise figure and ultra-low power consumption.