FDSOI Devices Research Articles

FDSOI Technology: A Power Efficient Solution Down to 10nm

This paper reports the technological details and the performance of the planar Fully Depleted SOI technology. Thanks to its intrinsic structure (SOI substrates, undoped channel, ultra-thin body and box thicknesses), FDSOI devices offer significant advantages over Bulk devices: better electrostatic control, better matching performance, improved drivability and better power efficiency. After the demonstration of a complete 28nm platform, scaling down to 14 and 10nm is highlighted in this paper.

Source and Drain Contact Module for FDSOI MOSFETs : Silicidation and Strain Engineering

Strained SiGe and SiC sources and drains are planned to be used in sub-28nm FDSOI devices in order to improve the carriers mobility. Consequently, silicide-induced relaxation of strained epitaxial layers is a key issue to address in order to fully benefit from the desired effects of strain engineering techniques. This paper deal with the impact of the silicidation process conditions on the strain of Si1-xGex:B layers (x=0.3 and 0.45) and SiC:P with [C]≤1,5%. We show that the strain of epitaxial layers is not affected by the silicidation in the case of Si0.7Ge0.3 and SiC, while a strong degradation of strain occurs with Si0.55Ge0.45. The strain evolution in the channel of a device at various stages of the silicidation process has been followed using dark field electron holography. We show that process parameters can be tuned in order to minimize the reduction of strain induced by the silicidation

Modeling of low frequency noise in FD SOI MOSFETs

In this paper, we present the modeling of low frequency noise of FD SOI devices in the front and back interface channel operations. We present an analytical model for the inversion charge power spectral density in FD SOI MOSFETs. This analytical model is valid for the different modes of operation of the device, in both the front and the back conduction regimes. The simulation results are compared to those obtained using our numerical model presented in a previous work and to experimental data. A very good agreement between both models and the measurements is obtained. We show that when only the back channel is activated, the influence of the front oxide noise contribution can be neglected.

New parameter extraction method based on split C–V measurements in FDSOI MOSFETs

A new parameter extraction methodology based on split C–V is proposed for FDSOI MOS devices. To this end, a detailed capacitance theoretical analysis is first conducted emphasizing the usefulness of the Maserjian function. Split C–V measurements carried out on various FDSOI CMOS technologies show that the Maserjian function exhibits a power law dependence with inversion charge as ∝Qi−2 whatever the carrier type and gate oxide thickness. This feature enables to confirm the validity of a two-parameter simple capacitance model and allows for a reliable MOSFET parameter extraction in FDSOI devices.

Current progress in modeling self-heating effects in FD SOI devices and nanowire transistors

In this paper we summarize 6 years of work on modeling self-heating effects in nano-scale devices at Arizona State University (ASU). We first describe the key features of the electro-thermal Monte Carlo device simulator (the two-dimensional and the three-dimensional version of the tool) and then we present series of representative simulation results that clearly illustrate the importance of self-heating in larger nanoscale devices made in silicon on insulator technology (SOI). Our simulation results also show that in the smallest devices considered the heat is in the contacts, not in the active channel region of the device. Therefore, integrated circuits get hotter due to larger density of devices but the device performance is only slightly degraded at the smallest device size. This is because of two factors: pronounced velocity overshoot effect and smaller thermal resistance of the buried oxide layer. Efficient removal of heat from the metal contacts is still an unsolved problem and can lead to a variety of non-desirable effects, including electromigration. We propose ways how heat can be effectively removed from the device by using silicon on diamond and silicon on AlN technologies. We also study the interplay of Coulomb interactions due to the presence of a random trap at the source end of the channel and the self-heating effects. We illustrate the influence of a positive and a negative trap on the magnitude of the on-current and the role of the potential barrier at the source end of the channel.

Characterization and modeling of capacitances in FD-SOI devices

Gate-to-channel capacitance Cgc(Vg) data obtained on FD-SOI MOS devices with gate lengths down to 35nm are first reported. Thus, a 2D numerical simulation procedure allowing to calculate the total device capacitance and parasitic capacitances is developed. This enabled us to discriminate the respective contributions of all parasitic components such as spacer, overlap, inner fringe and buried oxide capacitances in the structure.

Analysis of UTBOX 1T-DRAM Memory Cell at High Temperatures

This work investigates the behavior of Ultra Thin BOX (UTBOX) FDSOI devices used as a memory cell 1T-DRAM (single transistor dynamic random access memory) at high temperatures through 2D numerical simulations. The minimum drain voltage for the onset of the bipolar junction transistor (BJT) effect (VLatch) was obtained for various buried oxide thickness (tbox) and silicon film thickness (tSi). The simulation results clearly show that, when temperature increases, the VLatch, the sense margin current (ΔISENSE), the latch time (tLatch) and the retention time decreases.

Gate-induced drain leakage in FD-SOI devices: What the TFET teaches us about the MOSFET

This paper compares the gate-induced drain leakage (GIDL) in fully-depleted (FD) silicon-on-insulator (SOI) tunneling field effect transistor (TFET) and in standard metal-oxide-semiconductor FET (MOSFET) fabricated in the same process. The measurements show that the MOSFET GIDL current is lower than the GIDL in a TFET with the same junction doping, especially for devices with thick gate oxide and under low drain bias. A model describing lateral band-to-band tunneling (BTBT) is developed for GIDL in the FD-SOI TFET. By combining the model of gate-controllable tunneling diode in series with a field effect diode, we achieve an accurate picture of GIDL in FD-SOI MOSFETs.

(Invited) Strain Engineering for Fully-Depleted SOI Devices

Limitations of conventional strain engineering methods for fully-depleted SOI structure are reviewed and methods to extend these approaches to future FDSOI devices are discussed. The application of global strain engineering combined with biaxial to uniaxial strain conversion is shown to be promising. Finally, methods to utilize oxidation-induced strain engineering are introduced.

DC and low frequency noise characterization of FinFET devices

A detailed DC and LF noise characterization of FinFETs is carried out. Parameter extraction conducted at room and low temperature clearly indicates that the mobility is degraded at small gate length in sub 100 nm FinFETs, as was already found for GAA, FD-SOI and DG-MOS devices. By proper extraction technique, sidewall and top conductions are analyzed, showing that sidewall mobility is about 25–30% degraded as compared to the top surface conduction, likely resulting from Fin patterning-induced defects and/or crystal orientation difference. Trap density in high- k/metal gate stack is found much larger than in pure SiO 2 MOSFETs but with no further degradation at small Fin widths.

Back-Gate Influence on the Mobility Behavior in Ultrathin FD SOI Devices

The carrier mobility in advanced ultra-thin SOI transistors with n- and p-channels was measured using the Y-function and the transconductance peak methods. The mobilities at front channel and back channel were investigated as a function of the opposite gate bias and channel width. The results confirm that the mobility extracted from the Y-function is greatly overestimated when the opposite channel is activated. The experiments also show that the electron mobility is higher at the back channel than at the front channel. Finally, a decrease in mobility is observed in narrower channels.

Thermal Stability and Electrical Characteristics of Tungsten Nitride Gates in Metal–Oxide–Semiconductor Devices

Tungsten nitride (WNx) was investigated to be used as a metal gate of metal–oxide–semiconductor field effect transistors (MOSFETs). WNx films with various N/W atomic ratios were deposited on SiO2 and HfO2 by reactive sputter deposition at different N2/Ar ratio flows. Nitrogen concentration in WNx films increases rapidly with the N2/Ar gas ratio and tends to saturate. WNx films with nitrogen atomic ratio higher than 44% have a main phase of WN, and the WN phase is stable up to 800 °C. The higher-order WNx phase does not form even if the nitrogen concentration is as high as 61%. Many of the excess nitrogen atoms in WNx films are desorbed at temperatures below 766 °C. The excess nitrogen in WNx films can cause effective work function lowering. A weak Fermi-level pinning effect is observed on the HfO2 film. In this case, WNx is not suitable to be metal gate of bulk p-channel MOSFETs. Fully depleted silicon-on-insulator (FD SOI) devices require a work function of 0.2 eV from the midgap of the Si energy band. Therefore, a WNx/HfO2 gate stack can be applied to p-channel FD SOI devices. The good integrity of the WNx/HfO2 gate stack also suggests that WNx is a promising gate material.

Threshold Voltage Model of Short-Channel FD-SOI MOSFETs With Vertical Gaussian Profile

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A novel approximation of 2-D potential function perpendicular to the channel for fully depleted (FD) silicon-on-insulator (SOI) MOSFETs on films with vertical Gaussian profile is proposed in the paper, then an analytical threshold voltage model is derived. The model agrees well with the MEDICI numerical simulation results. It represents a feasible way to find the threshold voltage and gives some reference points in developing new 2-D models for nonuniform FD-SOI devices. </para>

Characterization of FD SOI devices and VCO’s on thin dielectric membranes under pressure

In this paper, silicon-on-insulator MOSFETs and ring oscillators are, for the first time, fabricated and characterized on 1.5 μm-thick multilayered dielectric membranes, as a preliminary study for pressure sensing systems. Stresses were mechanically applied on these membranes, evolving drain current changes up to 5% in the devices characteristics, according to their channel type and orientation with respect to the stress, as well as resonance frequency shifts of −0.8% and +2.5% for the voltage controlled oscillators. Finite element simulations were performed, showing that the stresses are maximized at the center of the membrane anchors and pointing out the location for the devices to provide the best sensitivity. Internal membrane stresses are considered and discussed.

Fully Depleted Silicon-on-Insulator nMOSFETs with Tensile Strained High Carbon Content Si1-yCy Channels

High carbon content Si1-yCy layers, with substitutional C concentration as high as 2% and almost no interstitial C atoms (<0.1%) have been grown by Reduced Pressure Chemical Vapour Deposition. The electrical Si1-yCy /Si/SiO2 interface properties have been investigated. It was demonstrated that low oxidation temperature has a beneficial effect on the interface state density as well as on the oxide quality. These high quality Si1-yCy layers have been used as the channel of n-type TiN metal gate FDSOI devices. The threshold voltage adjustment induced by the conduction band offset of Si1-yCy channel is clearly demonstrated.

A study of envelope functions in FD-SOI devices for non-parabolic bands

In this study we analyzed the envelope functions obtained by solving the effective-mass Schrodinger equation including the non-parabolicity of the valence band in p-type FD-SOI devices. In order to carry out this task, we used two different algorithms to solve the effective-mass Schrodinger equation in barriers, and calculated the envelope functions and eigenenergies yielded by these methods for several states along the subbands. This study enabled us to propose a method for selecting the most appropriate envelope functions for each subband. Finally, we quantified the differences in phonon and interface-roughness scattering rates resulting from using the envelope function proposed rather than that obtained by simpler approaches in barriers.

Ultralow-power CMOS/SOI Circuit Technology

We have introduced an example of a system that embodies the concept of a ubiquitous communication service and explained the importance of low power consumption in the communicator that will serve as the bridge between the real world and the network for real-time services in which sensor data is acquired every second. An effective solution to the problem of high energy efficiency is to employ the synergy of combining low-voltage analog circuit technology and FD-SOI devices. Taking advantage of that synergy to reduce the power consumption of the communicator during operation to about 10 mW and employing intermittent operation with an activity rate of less than 1% would make it possible to support operation for one year or more with a commercial coin-type lithium battery.

Reduced Hot Carrier Effects in Self-Aligned Ground-Plane FDSOI MOSFET’s

This paper reports the hot-carrier induced device degradation of fully depleted (FD) n-channel SOI MOSFETs with a self-aligned ground-plane electrode in the silicon substrate underneath the buried oxide. The ground-plane configuration is shown to reduce short-channel effects, BJT effects and hot-carrier effects. Based on measurements of hot-carrier degradation rate, it is predicted that the maximum allowable supply voltage of ground-plane FDSOI MOSFET is higher than that of FDSOI device without a ground plane.

2D ensemble Monte Carlo modelling of bulk and FD SOI MOSFETs: active layer thickness and noise performance

In this work, the RF and microwave noise performance of bulk and fully-depleted silicon-on-insulator (FD SOI) transistors with directly comparable topologies is investigated by means of an ensemble Monte Carlo simulator, and in the case of FD SOI devices, the influence of varying the active layer thickness is also studied. Intrinsic noise sources are calculated and analysed, and important figures of merit such as NFmin or Rn are also determined and evaluated. Moreover, a microscopic understanding of the noise phenomena is achieved, which is essential for the optimization of the transistors. FD SOI devices show a reduced influence of induced gate noise and drain noise as compared to the bulk transistor due to the minor influence of phonon scattering and energetic carriers at the pinch-off region. Whereas reducing the active layer thickness minimizes the effect of hot carriers in the noise parameters, it can lead to a degradation of other important high-frequency figures of merit such as gm or fT.

A physically based investigation of the small-signal behaviour of bulk and fully-depleted silicon-on-insulator MOSFETs for microwave applications

We present a Monte Carlo investigation of the dynamic performance of bulk and FD SOI MOSFET devices with one-to-one comparable topologies. The features of the simulator allow us to provide a complete comprehension of the transport phenomena and the main internal quantities that are connected to the small-signal behaviour of the devices at RF and microwave frequencies. In this way, the effect of the buried oxide and the variation of the active layer thickness on the static and dynamic characteristics of FD SOI MOSFETs are readily evaluated, and an exhaustive investigation of the physical basis of the dynamic performance is realized, thus clarifying the underlying differences between bulk and FD SOI transistors that can be used for the optimization of the devices. The parameters of the small-signal equivalent circuit are carefully analysed: important issues, such as the high frequency capacitive coupling to the substrate, the physical meaning of non-quasistatic parameters or the behaviour of figures of merit such as gm, fT and fmax are studied in detail. Furthermore, when scattering parameters are evaluated the kink effect in the S22 parameter at high frequencies has been checked to be much more pronounced in the case of FD SOI devices.