Abstract

A detailed DC and LF noise characterization of FinFETs is carried out. Parameter extraction conducted at room and low temperature clearly indicates that the mobility is degraded at small gate length in sub 100 nm FinFETs, as was already found for GAA, FD-SOI and DG-MOS devices. By proper extraction technique, sidewall and top conductions are analyzed, showing that sidewall mobility is about 25–30% degraded as compared to the top surface conduction, likely resulting from Fin patterning-induced defects and/or crystal orientation difference. Trap density in high- k/metal gate stack is found much larger than in pure SiO 2 MOSFETs but with no further degradation at small Fin widths.

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.