Electrical Characteristics Of MOSFETs Research Articles

The influence of radiation on the electrical characteristics of MOSFET and its revival by different annealing techniques

Defects originate in N-channel MOSFETs by exposing them to high-energy ions and 60Co gamma radiation separately to different radiation doses. The electrical variations in MOSFETs are characterized systematically before and after the influence of radiation on MOSFETs. The impact of 60Co gamma radiation on threshold voltage (V TH) and mobility (µ) characteristics of MOSFETs is more than the impact of high energy ions on MOSFETs. The annealing of electrical characteristics in the irradiated MOSFETs is studied systematically by isothermal and isochronal annealing techniques. The isochronal annealing technique is more preferable due to its high recovery rate than the isothermal annealing technique.

Combined nanoscale KPFM characterization and device simulation for the evaluation of the MOSFET variability related to metal gate workfunction fluctuations

In this work, a more realistic approximation based on 2D nanoscale experimental data obtained on a metal layer is presented to investigate the impact of the metal gate polycrystallinity on the MOSFET variability. The nanoscale data (obtained with a Kelvin Probe Force Microscope, KPFM) were introduced in a device simulator to analyze the effect of a TiN metal gate work functions (WF) fluctuations on the MOSFET electrical characteristics. The results demonstrate that the device characteristics are affected not only by the WF fluctuations, but also their spatial distribution, which is specially relevant in very small devices. The effect on these characteristics of the spatial distribution on the gate area of such fluctuations is also evaluated.

Impact of Semiconductor Permittivity Reduction on Electrical Characteristics of Nanoscale MOSFETs

The dielectric screening property of a semiconductor is very crucial for the electrical characteristics of a MOSFET, and which can be described mathematically by Poisson equation via the permittivity. While the theory and experiments have corroborated the permittivity reduction of nanoscale Si, this paper studies the electrical characteristics of MOSFETs considering the reduced channel permittivity by quantum transport simulations. It is found that the channel permittivity reduction may mitigate the short-channel effects, showing subthreshold swing improvement and threshold voltage shift of MOSFETs in nanoscale. Compared to quantization effects, the positive and negative impacts of the channel permittivity reduction on the devices in particularly nanoscale have been investigated. This paper elucidates the necessity of considering semiconductor permittivity reduction for nanoscale device design and simulations.

A comparison of 4 MeV Proton and Co-60 gamma irradiation induced degradation in the electrical characteristics of N-channel MOSFETs

N-channel depletion MOSFETs were irradiated with 4MeV Proton and Co-60 gamma radiation in the dose range of 100krad(Si) to 100Mrad(Si). The electrical characteristics of MOSFET such as threshold voltage (Vth), density of interface trapped charges (ΔNit), density of oxide trapped charges (ΔNot), transconductance (gm), mobility (μ), leakage current (IL) and drain saturation current (ID Sat) were studied as a function of dose. A considerable increase in ΔNit and ΔNot and decrease in Vth,gm, μ, and ID Sat was observed after irradiation. The results of 4MeV Proton irradiation were compared with that of Co-60 gamma radiation and it is found that the degradation is more for the devices irradiated with 4MeV Protons when compared with the Co-60 gamma radiation. This indicates that Protons induce more trapped charges in the field oxide region when compared to the gamma radiation.

Swift heavy ion irradiation and annealing studies on the I–V characteristics of N-channel depletion Metal–oxide–semiconductor field-effect transistors

N-channel depletion MOSFETs were irradiated with different swift heavy ions viz., 175 MeV Ni13+ ions, 140 MeV Si10+ ions, 100 MeV F8+ ions, 95 MeV O7+ ions and 48 MeV Li3+ ions in the same dose range of 100 krad–100 Mrad. The different electrical characteristics of MOSFETs were studied before and after irradiation and after annealing. The degradation and recovery mechanisms were studied systematically. It was found that around 80 % degradation in transconductance and mobility and almost 100 % recoveries in the electrical characteristics of irradiated MOSFETs after annealing.

Mobility degradation mechanisms of MOSFETs with a high-k dielectric layer.

The electrical characteristics of MOSFETs with a high-k dielectric layer were simulated by using a full three-dimensional technology computer-aided design simulator. The MOSFETs leakage current increased when their size decreased. The mobility variation mechanisms due to the polarization variation with the positive fixed charges in the high-k dielectric layer and with the negative trap charges in the SiO2 layer were clarified by using a modified mobility model of the universal model taking into account remote phonon scattering effects. The induced polarization in the high-k dielectric layer was dominantly attributed to the magnitude and the polarity of the charges in an interfacial layer. The mobility degradation was dominantly attributed to the polarization effects. The mobility values of the channel region in the MOSFETs, calculated by using the modified mobility model, were in reasonable agreement with their real mobility magnitudes. This result improves the enhancement of the electrical characteristic of the MOSFETs with a high-k layer.

Stress assessment for device performance in three-dimensional IC: linked package-scale/die-scale/feature-scale simulation flow

Potential challenges with managing mechanical stress and the consequent effects on device performance for advanced three-dimensional (3-D) IC technologies are outlined. The growing need in a simulation-based design verification flow capable of analyzing a design of 3-D IC stacks and detecting across-die out-of-spec variations in MOSFET electrical characteristics caused by the die thinning and stacking-induced mechanical stress is addressed. The development of a multiscale simulation methodology for managing mechanical stresses during a sequence of designs of 3-D IC dies, stacks, and packages is focused. A set of physics-based compact models for a multiscale simulation is proposed to assess the mechanical stress across the device layers in silicon chips stacked and packaged with the 2.5D interposer-based, and true 3-D through silicon via-based technology. A simulation flow is developed for the hot-spot checking in different types of devices/circuits such as digital, analog, analog matching, memory, IO, characterized by different sensitivities to the stress-induced mobility variations. A calibration technique based on fitting to measured electrical characteristics of the test-chip devices is presented. The limited characterization or measurement capabilities for 3-D IC stacks and a strict “good die” requirement make this type of analysis critical in order to achieve an acceptable level of functional and parametric yield.

Enhanced Hole Mobility and Low $Tinv$ for pMOSFET by a Novel Epitaxial Si/Ge Superlattice Channel

Since the SiGe or Ge channel materials are desirable to enhance the carrier mobility degraded by ultrathin high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> gate dielectric, the pMOSFET device with novel superlattice (SL) SiGe channels is proposed in this letter. Experimental results show that the electrical characteristics of MOSFET can be obviously improved by an SL virtual substrate. The peak hole mobility of the pMOSFET device with SL is enhanced by about 100% as compared to that with the Si one. The on-off ratio of the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Id</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Vg</i> curve is beyond eight orders, and the electrical thickness in inversion ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Tinv</i> ) value of the gate dielectric can be ~1.4 nm. The source/drain activation temperature of 650°C is particularly suitable to high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> dielectric process.

Improving the electrical characteristics of MOS transistors with CeO2/La2O3 stacked gate dielectric

In this work, the electrical characteristics of MOSFETs with CeO2/La2O3 gate dielectric stacks, where it was shown to have much lower amount of oxygen vacancy, were studied. We found that the negative threshold voltage shift in the La2O3-only transistors can be significantly suppressed. This improvement is attributed to the reduction of oxide charge density and to the dipole at the Si/La2O3 interface. Significant enhancement in channel mobility was also found for both NMOS and PMOS transistors. This latter improvement should be due to the silicon oxidation taking place at the La2O3/Si interface with the available of extra oxygen atoms from the CeO2 layer. We further found that the subthreshold slopes for NMOS and PMOS transistors with 2.5μm gate length were reduced to about 72mV/dec, which are significantly smaller than those of transistors without using CeO2 capping layer. This observation further confirms that the CeO2 capping layer also affects the La2O3/Si interface properties.

A new method for stable numerical differentiation

In this paper, we proposed a new algorithm for stable numerical differentiation by optimizing node intervals. With the algorithm, noise-free differentiated values can be extracted within one-percent error. By overcoming noise problem due to numerical differentiation process, our algorithm can easily extract the differentiated values. Also, it can be extended to high order differentiation. To confirm the proposed algorithm, we applied it to the analysis of MOSFET electrical characteristics. It will provide us with a useful analysis tool in the field of parameter extraction from numerical data such as device characterization.

Effects of N Implantation before Gate Oxidation on the Performance of 4H-SiC MOSFET

The electrical characteristics of MOSFETs fabricated on 4H-SiC with a process based on N implantation in the channel region before the growth of the gate oxide are reported as a function of the N concentration at the SiO2/SiC interface up to 6  1019 cm-3. The field effect mobility improves with increasing N concentration. At room temperature values change from 4 cm2/Vs for the not implanted sample up to 42 cm2/Vs for the sample with the highest N concentration. Furthermore, the field effect mobility increases with temperature and presents values above 60 cm2/Vs at 200 °C. The MOSFETs with the better electrical characteristics (higher mobility, lower threshold voltage, lower subthreshold swing) were fabricated by a low thermal budget oxidation process, thank to the use of a high N implantation dose able to produce an amorphous SiC surface layer. A strong correlation among the increasing of the N concentration at the SiO2/SiC interface, the reduction of the interface state density located near the conduction band and the improvement of the MOSFETs performance was obtained.

Data Analysis Technique of Atomic Force Microscopy for Atomically Flat Silicon Surfaces

A data analysis technology of atomic force microscopy for atomically flat silicon surfaces has been developed. Atomically flat silicon-surfaces composed of atomic terraces and steps are obtained on (100) orientation 200 mm diameter wafers by annealing in pure argon ambience at 1,200°C for 30 minutes. Atomically flat silicon surfaces are lead to improve the MOS inversion layer mobility and current drivability of MOSFETs and to decrease the fluctuations in electrical characteristics of MOSFETs. It is important to realize the technology that evaluates the flatness and the uniformity of atomically flat silicon surfaces. The off direction angle is calculated by using two straight edge lines selected from measurement data. And the off angle is calculated from average atomic terrace width under assumption that height difference between neighboring terraces is equal to the step height, 0.135 nm, of (100) silicon surface. The analyzing of flatness of each terrace can be realized by converting the measurement data using the off direction angle and the off angle. And, the average roughness of each terrace is about 0.017-0.023 nm. Therefore, the roughness and the uniformity of each terrace can be evaluated by this proposed technique.

Lifetime estimation of analog circuits from the electrical characteristics of stressed MOSFETs

In this work, the impact of dielectric degradation in the MOSFET electrical characteristics after different levels of Fowler-Nordheim (FN) stress has been studied. A decrease in I SAT and an increase of V T have been observed. The interface trap density has been extracted from the sub-threshold slope of I D– V GS curves. The results show a direct relation between the generated interfacial traps and the observed changes in saturation current and threshold voltage. The wear out effects in the devices have been extrapolated to operation voltages, pointing out that the transistors can fulfill the reliability criteria, even when working in analog applications.

Impact of defects on the high- κ/MG stack: The electrical characterization challenge

The integration of high- κ dielectrics in MOSFET devices is beset by many problems. In this paper a review on the impact of defects in high- κ materials on the MOSFET electrical characteristics is presented. Beside the quality of the bulk of the dielectric itself, the interfaces between the high- κ and the interfacial oxide layer and the gate electrode are of crucial importance. When poly-Si is used as gate electrode, the defects at the poly-Si/high- κ interface control the band alignment as well as the gate depletion. The quality and thickness of the interfacial SiO 2 controls both the carrier mobility in the channel as well as the kinetics of charging and discharging of pre-existing high- κ defects. The quality of the interfacial layer has also important consequences for reliability specifications like negative bias instability and dielectric breakdown.

Highly reliable high- k gate dielectrics with gradual Hf-profile in the HfO 2/SiO 2 interface region

We proposed a gradually profiled-Hf interface as a design concept of the high- k/SiO 2 interface region for improving the high- k stack dielectric reliability by controlling the compositional profile between the high- k bulk layer and the underlying SiO 2 layer. This gradually profiled-Hf interface named as the constituent gradual interface layer CG-IL is fabricated by the Hf diffusion into the underlying SiO 2 with repeating the sequence of thin HfO 2 film deposition and annealing through the “layer-by-layer deposition and annealing (LL-D & A)” technique. The electrical characteristics of MOSFETs with the CG-IL and TaN gate were evaluated. Also, as a reference, we fabricated the conventional HfO 2/SiO 2 bi-layer structure MOSFETs. The gate leakage current through the CG-IL structure is more than one order of magnitude smaller than that of the bi-layer structure, despite of the thinner EOT. Also, the dielectric breakdown voltage of MOS capacitors with the CG-IL structure is higher than that of the conventional bi-layer structure. Furthermore, the distribution of time-to-breakdown of MOS capacitors with GC-IL structure is significantly improved compared with that of the bi-layer structure. We consider that the CG-IL structure forms the robust interfacial structure between HfO 2 and SiO 2, by mainly reducing the defects states localized around the HfO 2/SiO 2 interface region, and is a promising structure for achieving the highly reliable high- k gate stacks.

Optimisation of an electronic amplifier applied to electrolyte/insulator/semiconductor structure

This paper reports on the final development of a MOSFET-based amplifier for the electrical characterisation of chemical field-effect capacitors (ChemFEC) based on electrolyte/insulator/semiconductor (EIS) capacitive structure. Experimental demonstration is performed through the study of SiO 2/Si 3N 4 ion sensitive field-effect capacitor (ISFEC) sensors for pH measurement. This study deals with the amplification's properties according to the ISFEC and MOSFET electrical characteristics. Thus, the ISFEC transition from the accumulation to the inversion regime is shown to be responsible for a non-linear phenomenon. Nevertheless, thanks to a compromise between the ISFEC flat-band voltage and the MOSFET threshold voltage, linear responses are evidenced on the [2–12] pH range. Thus, the non-linear phenomenon observed in previous works is clarified. The detection structure evidences linear responses, which is an essential parameter for sensors. Finally, high detection sensitivities are obtained on a small pH range due to this non-linearity.

Investigation of the proportional difference characteristics of MOSFETs

A proportional difference operator method has been presented to study the electrical characteristics of MOSFETs in all the operating regimes. It is shown that the proportional difference drain current versus the drain voltage exhibits a spectrum feature in all regions of operation including the subthreshold regime and the saturation regime. The amplitude of the spectrum peak is related to the effective carrier mobility, and the spectrum peak position responds to the voltage constants in each operating region (including the subthreshold and saturation regime) of a MOSFET. This then enables the more important statistic performance of MOSFETs to be evaluated using the proportional difference operator method. Analytical expressions for computing these parameters (such as effective carrier mobility, thermal voltage, threshold voltage etc.) have been derived and experimental results have been presented.

Hot-carrier reliability of ultra-thin gate oxide CMOS

Hot-carrier degradation on electrical characteristics of MOSFETs in the direct-tunneling regime of the gate oxide was investigated under a wide range of conditions, namely stress bias, oxide thickness, gate length, and channel-type dependence. It was confirmed that the transconductance degradation of n-MOSFETs with thinner gate oxides is smaller than that of thicker gate oxide MOSFETs, in spite of larger gate direct-tunneling leakage current and larger hot-carrier generation. For p-MOSFETs, little degradation was observed under all conditions of stress bias, oxide thickness, and gate length.

Quasi Drift and Quasi Diffusion: A Grain size Dependent Polysilicon Tft Model

AbstractMost of the models for Thin Film Transistors take no account of the way that electrons move across grain boundaries. The purpose of this work is to produce an analytical model, physically based, that takes account of both the change in height of the potential barriers that separate the grains, and the change of carrier density in the grains with gate voltage. The high current and subthreshold regions are treated. The model enables the change of field effect mobility with grain size and temperature to be determined. Two closed form expressions are provided which should be of value to both device and circuit designers, as well as providing insight to the physical processes occurring in such devices. They form a close analogy with the electrical characteristics of MOSFETs on crystalline silicon, diffusion and drift being replaced by quasi-diffusion and primary quasi-drift.

Fabrication of sub-50-nm gate length n-metal–oxide–semiconductor field effect transistors and their electrical characteristics

A method of fabricating 40-nm gate-length n-metal–oxide–semiconductor field effect transistors (MOSFETs) is described in detail. The fabrication of MOSFETs with gate lengths of this order poses two major problems: how to fabricate such small-geometry gate electrodes, and how to fabricate the ultrashallow source and drain junctions required. Two special techniques are used to overcome these problems: a resist-thinning process using isotropic oxygen plasma ashing for the fabrication of the gate electrodes, and a process of solid-phase diffusion from phosphorus-doped silicated-glass gate sidewalls for fabrication of the source and drain junctions. The resulting 40-nm gate electrodes and ultrashallow 10-nm junctions have an adequate impurity concentration and have been shown to function successfully. It has been confirmed that these 40-nm gate-length n-MOSFETs have good electrical characteristics at room temperature. Certain details of small-geometry MOSFET electrical characteristics are studied using these devices.