Impact of defects on the high- κ/MG stack: The electrical characterization challenge

Abstract

The integration of high- κ dielectrics in MOSFET devices is beset by many problems. In this paper a review on the impact of defects in high- κ materials on the MOSFET electrical characteristics is presented. Beside the quality of the bulk of the dielectric itself, the interfaces between the high- κ and the interfacial oxide layer and the gate electrode are of crucial importance. When poly-Si is used as gate electrode, the defects at the poly-Si/high- κ interface control the band alignment as well as the gate depletion. The quality and thickness of the interfacial SiO 2 controls both the carrier mobility in the channel as well as the kinetics of charging and discharging of pre-existing high- κ defects. The quality of the interfacial layer has also important consequences for reliability specifications like negative bias instability and dielectric breakdown.