Abstract
Potential challenges with managing mechanical stress and the consequent effects on device performance for advanced three-dimensional (3-D) IC technologies are outlined. The growing need in a simulation-based design verification flow capable of analyzing a design of 3-D IC stacks and detecting across-die out-of-spec variations in MOSFET electrical characteristics caused by the die thinning and stacking-induced mechanical stress is addressed. The development of a multiscale simulation methodology for managing mechanical stresses during a sequence of designs of 3-D IC dies, stacks, and packages is focused. A set of physics-based compact models for a multiscale simulation is proposed to assess the mechanical stress across the device layers in silicon chips stacked and packaged with the 2.5D interposer-based, and true 3-D through silicon via-based technology. A simulation flow is developed for the hot-spot checking in different types of devices/circuits such as digital, analog, analog matching, memory, IO, characterized by different sensitivities to the stress-induced mobility variations. A calibration technique based on fitting to measured electrical characteristics of the test-chip devices is presented. The limited characterization or measurement capabilities for 3-D IC stacks and a strict “good die” requirement make this type of analysis critical in order to achieve an acceptable level of functional and parametric yield.
Highlights
It is a common understanding that the motivation for 3-D IC integration is a mixture of economic and technical requirements, summarized within the term “More than Moore.”[1,2,3] Three-dimensional (3-D) IC stacking technologies, employing thinned wafer/through silicon via (TSV) structures, are novel solutions that result in reduced floor space, higher bandwidth, and reduced energy consumption
This paper describes the recently developed physicsbased simulator that predicts variation in transistor’s electrical characteristics, caused by chip–package interaction (CPI)
The tool is capable of analyzing any 3-D IC die stack design with regard to out-of-spec variations in device electrical characteristics caused by mechanical stress generated by warpages of the stacked dies, by solder bumps pressure generated in a course of die stacking, as well as by mismatch of thermomechanical properties of TSV and silicon die bulk
Summary
It is a common understanding that the motivation for 3-D IC integration is a mixture of economic and technical requirements, summarized within the term “More than Moore.”[1,2,3] Three-dimensional (3-D) IC stacking technologies (including 2.5D interposer-based approaches), employing thinned wafer/through silicon via (TSV) structures, are novel solutions that result in reduced floor space, higher bandwidth, and reduced energy consumption. Due to thin die bending; bump and TSV scale (i.e., 10 to 100 μm) local stress variations, which are induced by the package component assembly; device scale (10 to 100 nm) variations due to transistor layer nonuniformity Traditional methods such as finite-difference analysis and finite-element analysis (FEA) cannot be employed for a simulation of the transistor channel stress distribution across a die due to the size of a model, which can reach hundreds of millions degrees of freedom. Details of chip structures (layer information, layout, etc.) have not been considered, and the problem with calculating the transistor-to-transistor intrachannel stress variation and consequent variation in transistor electrical characteristics has not been addressed yet.[6] In order to be able to consider these effects, the stress simulation methodology should be capable to resolve scales of the order of a transistor size (approximately nanometers) and, to account for all major internal (layout-induced) and external (e.g., packaging) stress sources affecting a particular device. The simulator provides an interface between layout formats (GDS II, OASIS) and FEA-based package-scale models
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