Enhanced Hole Mobility and Low $Tinv$ for pMOSFET by a Novel Epitaxial Si/Ge Superlattice Channel

Abstract

Since the SiGe or Ge channel materials are desirable to enhance the carrier mobility degraded by ultrathin high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> gate dielectric, the pMOSFET device with novel superlattice (SL) SiGe channels is proposed in this letter. Experimental results show that the electrical characteristics of MOSFET can be obviously improved by an SL virtual substrate. The peak hole mobility of the pMOSFET device with SL is enhanced by about 100% as compared to that with the Si one. The on-off ratio of the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Id</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Vg</i> curve is beyond eight orders, and the electrical thickness in inversion ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Tinv</i> ) value of the gate dielectric can be ~1.4 nm. The source/drain activation temperature of 650°C is particularly suitable to high- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> dielectric process.