Improving the electrical characteristics of MOS transistors with CeO2/La2O3 stacked gate dielectric

Abstract

In this work, the electrical characteristics of MOSFETs with CeO2/La2O3 gate dielectric stacks, where it was shown to have much lower amount of oxygen vacancy, were studied. We found that the negative threshold voltage shift in the La2O3-only transistors can be significantly suppressed. This improvement is attributed to the reduction of oxide charge density and to the dipole at the Si/La2O3 interface. Significant enhancement in channel mobility was also found for both NMOS and PMOS transistors. This latter improvement should be due to the silicon oxidation taking place at the La2O3/Si interface with the available of extra oxygen atoms from the CeO2 layer. We further found that the subthreshold slopes for NMOS and PMOS transistors with 2.5μm gate length were reduced to about 72mV/dec, which are significantly smaller than those of transistors without using CeO2 capping layer. This observation further confirms that the CeO2 capping layer also affects the La2O3/Si interface properties.