Vertically Stacked High Mobility GeSi nGAAFETs

Abstract

Si FinFET architecture has been used in mass production in the industry for advanced technology nodes. Thin and tall fin for high drive current is needed for further scaling by FinFETs. However, fin aspect ratio and lithography limitation may be problematic issues. Recently, vertically stacked channel GAAFETs become good candidates to achieve better power-performance properties than FinFETs for the given footprint. The evolution to the stacked GAAFETs mitigates the patterning challenges by well-controlled epitaxy and high etching selectivity to achieve high performance and good electrostatics. The state-of-the-art stacked Si channel n/pGAAFETs and stacked Ge channel pGAAFETs have been reported. In this study, we demonstrate vertically stacked tensily strained GeSi nGAAFETs. The stacked GeSi nGAAFETs provide a possible solution to achieve high performance and to improve the electrostatics for Ge-based channel GAAFETs.The Ge/Ge0.85Si0.15 and Ge/Ge0.98Si0.02 multilayers are epitaxially grown on SOI substrates by CVD epitaxy. Ge buffer layers and sacrificial layers are not only used to achieve etching selectivity over GeSi layers to form the vertically stacked GeSi channels, but also used to provide tensile strain for GeSi n channels. Undoped channels and heavily doped sacrificial layers are used to reduce the impurity scattering and S/D resistance, respectively. The following PMA, laser annealing, and NiGe contacts formation for nFETs can further reduce the parasitic resistance to reveal the intrinsic merit of the high mobility GeSi channels.For GeSi nFETs, [Ge] larger than 85% in GeSi can ensure L valley conduction for small conductive effective mass to achieve high mobility. The △Ec between GeSi and Si is nearly zero and can be negligible. As a result, electron can flow through stacked GeSi channels and Si channel underneath for the nFETs. An engineering solution is provided to improve the electrostatic behaviors of Ge-based channels GAAFETs. We demonstrate the vertically stacked Ge0.85Si0.15 channels above a Si channel, which has good subthreshold behaviors. The VT difference between Ge0.85Si0.15 and Si can be tuned by the channel size optimizing. By narrowing the Ge0.85Si0.15 channel size to 5nm, the bandgap can be increased by quantum confinement and the short channel effect can be suppressed. As a result, more positive VT for Ge0.85Si0.15 than Si is observed. Therefore, the underneath Si channel with good electrostatic turn on first and dominate the subthreshold region. Good SS=76mV/dec and low DIBL=36mV/V are obtained due to low Dit and good short channel control. IOFF is also dramatically reduced and the ION/IOFF is improved to be 1.2E7 thanks to the increase of the bandgap and the improved short channel control for the narrow Ge0.85Si0.15 channels. The improved flicker noise of optimized channel size also indicates the enhanced reliability.To increase [Ge] in channel layers for mobility enhancement, Si incorporation as small as 2% into Ge can achieve sufficient etching selectivity of heavily phosphorus-doped Ge sacrificial layers over undoped Ge0.98Si0.02 to form two stacked Ge0.98Si0.02 nanowire channels, and introduce 0.27% uniaxial tensile strain for the electron mobility enhancement. The alloy scattering is still minimal for 2% Si. An additional 800oC anneal after the Ge buffer growth further improves the epi quality by confining misfit dislocations near the Ge buffer/Si interface. However, the Dit at Si underneath channel/dielectrics interface may be poor due to misfit dislocations confinement. As a result, the parasitic Ge/Si channel underneath the Ge0.98Si0.02 channels is completely removed by optimized etching. The distinct photoresponse of the floating channels and the parasitic channels can be a signature and provide a non-destructive method to check the existence of the parasitic channels. The photoresponse of the sole parasitic channel mainly shows the photocurrent (Iph), while the photoresponse of the sole floating channels without parasitic channel yields the negative threshold voltage shift (ΔVT) for nFETs. The device with both floating channels and the parasitic channel shows both photocurrent and negative threshold voltage shift under exposure. ION can be enhanced by scaled LG and large channel cross section. Record ION of 48μA per stack at VOV=VDS=0.5V and record Q (Gm,max/SSSAT) of 8.3 at VDS=0.5V with LG=40 nm are achieved among Ge nFETs.CVD grown Ge nGAAFET is compatible with Si technology. Excellent electrical characteristics are achieved and the results are comparable to mature Si nFETs. Indicating vertically stacked high mobility channel is promising candidate for CMOS applications in the future technology nodes to further extend the Moore’s law.Acknowledgements: This work is supported by MOST (MOST 109-2218-E-002-031- and 108-2622-8-002-016-) and MOE (NTU-CC-109L891601), Taiwan. The support from Taiwan Semiconductor Research Institute is also highly appreciated.