(Invited) Vertically Stacked n Channel and p Channel Transistors

Abstract

The Si FinFET architecture has been used in mass production in the industry for several technology nodes. Recently, the horizontal stacked channel GAAFET becomes a good candidate to achieve better power-performance properties than FinFETs in a certain area due to the promise of well controlled epitaxy, selective etching, and GAA nature. The state-of-the-art stacked Si channel n/pGAAFETs and stacked Ge channel pGAAFETs have been reported. In this study, we demonstrate the CVD grown, vertically-stacked strained GeSi channels for nGAAFETs and GeSn channels for pGAAFETs. The stacked GeSi nGAAFETs provide a possible solution to improve the electrostatics for Ge-based channel GAAFETs while the stacked GeSn pGAAFETs has record high ION and Gm with highly competitive subthreshold behaviors among GeSn pFinFETs and pGAAFETs. In addition, record low contact resistivity (4.4x10-10 ohm-cm2) to Ge using in-situ B and Sn incorporation by CVD is also demonstrated with low thermal budget (≦400oC) and without any Ga doping. The Ge/Ge0.85Si0.15 and Ge/Ge0.91Sn0.09 multi layers are epitaxially grown on SOI substrates by CVD. Ge buffer layers and sacrificial layers are not only used to be selectively etched in preference to GeSi and GeSn to form the vertical stacked GeSi channels and GeSn channels, but also to stress both GeSi N-channels tensily and GeSn P-channels compressively, respectively. The high temperature anneal for the buffer can confine the dislocations at the bottom of Ge buffer and reduce the defect density in the channels to improve the device performance. The heavy in-situ doping of source and drain, post metal annealing, laser annealing for nFETs, and NiGe/ PtGeSn formation can reduce the parasitic resistance to reveal the intrinsic merit of the high mobility GeSi and GeSn channels. For GeSi nFETs, rhe △Ec between GeSi and Si is nearly zero. As a result, electron can flow through stacked GeSi channels and Si channel underneath for the nFETs. The Vt difference between GeSi and Si can be tuned by the channel size optimizing. By narrowing the GeSi channel size to 5nm, the bandgap can be increased by quantum confinement and the short channel effect can be suppressed. As a result, more positive Vt for GeSi than Si is observed. The Si channel turn on first with good SS=76mV/dec and DIBL=36mV/V due to low Dit and good short channel control. Ioff is also dramatically reduced and the Ion/Ioff are improved to be 1.2E7 thanks to the increase of the bandgap and the improved short channel control for the narrow GeSi channels. The improved flicker noise also indicates the enhanced reliability. For GeSn pFETs, the {111} plane has high mobility, low dangling bond density, low Dit, and better gate control than the rectangular channel. Vertically stacked triangular Ge0.91Sn0.09 pGAAFETs with compressive strain of ~2% in the channel and low surface roughness are achieved by orientation dependent etching on natural etching stop {111} plane by the optimized etching process. The 22% reduction of SSlin=84mV/dec, 50% improvement of ION=120mA/mm at VOV=VDS=-0.5V, and 71% improvement of Gm=312mS/mm at VDS=-0.5V are achieved as compared to our previous work of 3 stacked Ge0.93Sn0.07 nanosheets. The device has the record ION of 19.3mA per stack at VOV= VDS=-0.5V and record Gm,max of 50.2mS per stack at VDS=-0.5V with competitive subthreshold behaviors among GeSn pFinFETs and pGAAFETs. For the p-type contact resistivity (ρc) reduction, B (>1x1021cm-3) and Sn (>12%) segregations at the Ti/GeSn:B interface are used to reduce the hole tunneling distance and the Schottky barrier height of holes, respectively. The GeSn:B is grown by CVD using Ge2H6, SnCl4, and B2H6 in H2 ambient at ≦320oC. Due to the Sn segregation, there is no need to grow high-[Sn] GeSn layer for the ρc reduction, which makes the pseudomorphic growth of the compressively strained GeSn possible. After metal deposition at elevated temperature and 400oC annealing, the ρc of 4.4x10-10 ohm-cm2 is achieved. Ge nGAAFETs, GeSn pGAAFETs, and the S/D with extremely low contact resistivity fabricated by CVD growth and optimized process are compatible with Si technologies and becomes promising candidates for CMOS applications in the future technology nodes. Acknowledgements: The MOST (107-2218-E-002-044-, 107-2622-8-002-018) and MOE (NTU-CC-108L891701), Taiwan. The support from Taiwan Semiconductor Research Institute is also highly appreciated.