Negative Capacitance Effect Research Articles

Physical Cause and Impact of Negative Capacitance Effect in Ferroelectric P(VDF-TrFE) Gate Stack and Its Application to Landau Transistor

A novel approach to overcome Boltzmann’s tyranny is to exploit the negative capacitance (NC) effect found naturally in many ferroelectric (FE) materials. We apply a set of coupled equations based on electrostatics, Kirchoff’s law, and a well-calibrated Ginzburg-Landau-Khalatnikov technology computer-aided design (TCAD) model to simulate an organic FE poly(vinylidene fluoride-co-trifluoroethylene) [P(VDF-TrFE)]-based resistor metal-FE-metal (R-MFM) series circuit and a Landau transistor (LT) exhibiting sub-60 mV/decade subthreshold swing (SS). TCAD simulation parameters for P(VDF-TrFE) are derived from the reported experimental polarization versus voltage characteristics using Landau theory. Unlike oxide FEs, the P(VDF-TrFE)-based R-MFM series circuit can exploit the NC effect at a lower supply voltage (VG) of ±0.5 V with little energy dissipation of ~2.7 fJ through R. Our simulation results show an 84.89% reduction in the P(VDF-TrFE)’s coercivity concerning the oxide FE. We show that the underlying mechanism of the NC effect is directly related to FE polarization (FE-P) switching. The NC effect occurs only when the FE-P is in the negative curvature of the P(VDF-TrFE)’s free energy landscape. The NC effect is explored in terms of VG, FE thickness, domain variations, R, and dipole switching resistivity. The influence of R variation on the NC time (δt) is investigated at 100 kHz. We can observe that δt and R have a linear relationship. As R approaches zero, we determined that the inherent FE-P switching speed exclusively restricts the NC effect. Finally, a 32 nm P(VDF-TrFE) LT provides a minimal SS of 23.39 mV/decade, 74.92% less than its CMOS counterpart. Therefore, the proposed organic MFM stack could open the path for developing beyond CMOS transistor technology operating in sub-60 mV/decade.

Whither Steady-State Negative Capacitance of a Ferroelectric Film?

We theoretically explore mechanisms that can potentially give rise to steady-state negative capacitance in a uniaxial ferroelectric film stabilized by a dielectric layer. The analytical expressions for the steady-state capacitance of a single-domain state are derived within Landau-Ginzburg-Devonshire approach and used to study the state stability vs. the domain splitting as a function of dielectric layer thickness. Analytical expressions for the critical thickness of the dielectric layer, polarization amplitude, equilibrium domain period and susceptibility are obtained and corroborated by finite element modelling. In the absence of screening charges neither single-domain, nor poly-domain states can exhibit globally-detectable steady-state negative capacitance. We further explore the possible effects of nonlinear screening at the ferroelectric-dielectric interface and show that if at least one of the screening charges is very slow, the total polarization dynamics can exhibit complex time- and voltage dependent behaviors that can be interpreted as a negative capacitance. In this setting, the negative capacitance effect is accompanied by almost zero dielectric susceptibility in a wide voltage range and low frequencies. These results may help to elucidate the fundamental dispute about the possible origin of the quasi-steady-state negative capacitance in thin ferroelectric films, and identify materials systems that can give rise to this behavior.

Mitigating DIBL and Short-Channel Effects for III-V FinFETs With Negative-Capacitance Effects

This paper, based on the IRDS 2022 technology node, investigates the DIBL and short-channel effects for InGaAs negative-capacitance FinFETs (NC-FinFETs) through a theoretical subthreshold drain current model considering key effects including negative capacitance, quantum confinement and source-to-drain tunneling. Due to the impact of negative capacitance on the source-to-drain potential profile, tunneling distance and its drain-bias dependence, the short-channel effects can be substantially improved for InGaAs NC-FinFETs. Our study indicates that, with the larger NC effect of the III-V channel, the gap in DIBL and subthreshold swing between InGaAs and Si FinFETs in the sub-20 nm gate-length regime can become much closer. Our study may provide insights for future supply-voltage/power scaling of logic devices with high-mobility channel.

Analysis of drain induced barrier lowering for junctionless double gate MOSFET using ferroelectric negative capacitance effect

<abstract> <p>We analyze the drain induced barrier lowering (DIBL) of a negative capacitance (NC) FET using a gate structure such as a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) for a junctionless double gate (JLDG) FET. NC FETs show negative DIBL characteristics according to the ferroelectric thickness. To elucidate the cause of such negative DIBL, the DIBLs are obtained by the second derivative method using the 2D potential distribution and drain current-gate voltage curve. The analytical DIBL model is also presented for easy observation of the DIBL of NC FET. It has been found that the results of this analytical DIBL model are very similar to those of the second derivative method. The results of this analytical DIBL model are also in good agreement with the results of TCAD. As a result, it was found that the negative DIBL phenomenon is caused by the change according to the drain voltage of the charge existing in the ferroelectric material. The negative DIBL phenomenon easily occurred as the ferroelectric thickness increased and the thickness of SiO<sub>2</sub> used as an insulator decreases.</p> </abstract>

Numerical Investigations of Nanowire Gate-All-Around Negative Capacitance GaAs/InN Tunnel FET

We demonstrated a nanowire gate-all-around (GAA) negative capacitance (NC) tunnel field-effect transistor (TFET) based on the GaAs/InN heterostructure using TCAD simulation. In the gate stacking, we proposed a tri-layer HfO₂/TiO₂/HfO₂ as a high-K dielectric and hafnium zirconium oxide (HZO) as a ferroelectric (FE) layer. The proposed GAA-TFET overcomes the thermionic limitation (60 mV/decade) of conventional MOSFETs&#x2019; subthreshold swing (SS) thanks to its improved electrostatic control and quantum mechanical tunneling. Simultaneously, the NC state of ferroelectric materials improves TFET performance by exploiting differential amplification of the gate voltage under certain conditions. The most surprising discoveries of this device, which outperforms all previous results, are the very high <inline-formula> <tex-math notation="LaTeX">$I_{ON}/I_{OFF}$ </tex-math></inline-formula> ratio on the order of 10¹¹ and the enormous on-state current of 135 <inline-formula> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula>. The incorporation of the NC effect with a 9 nm HZO results in the lowest <i>SS</i> of 20.56 mV/dec (52.38&#x0025; lower than baseline TFET) and the highest voltage gain of 6.58. Furthermore, the output characteristics revealed a large transconductance (<inline-formula> <tex-math notation="LaTeX">$g_{m}$ </tex-math></inline-formula>) of 7.87 mS (10³ order higher than the baseline TFET), drain-induced barrier lowering (DIBL) of 9.7 mV, and a threshold voltage of 0.53 V (37.65&#x0025; lower than baseline TFET), all of which are significant. Thus, all of the results indicate that the proposed device structure may lead to a new route for electronic devices, creating higher speed and lower power consumption.

The Impact of Dopant on the Dielectric Properties of Metal-Semiconductor With ZnFe2O4 Doped Organic Polymer Nanocomposites Interlayer

In this research, the dielectric characteristics of fabricated Al/(ZnFe <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> -PVA)/p-Si structures have been investigated in wide range frequency and voltage. Thus, by deriving capacitance-conductance (C-G/ω) measurements the main parameters of the metal-polymer-semiconductor (MPS) structure such as complex dielectric constants (ϵ' and ϵ''), loss tangent (tanδ), complex electric modulus (M' and M'') and ac electrical conductivity (σ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ac</sub> ), were acquired at frequency and voltage ranges of 1 kHz - 1MHz and (±5V). As a result of the experiment, it was observed that the presence of negative capacitance (NC) at low frequencies differently affects the dielectric properties of the structure. Although the NC effect disappeared at high frequencies by the reduction of the effect of many parameters such as series resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ss</sub> ) and interface states (N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ss</sub> ) with frequency increment, the dielectric properties of the structure varied especially in the reverse bias region. Ultimately, it has been observed that the dielectric properties of the structure are highly dependent on frequency, voltage, N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ss</sub> , and polarization.

An all two-dimensional vertical heterostructure graphene/CuInP2S6/MoS2 for negative capacitance field effect transistor

As scaling down the size of metal oxide semiconductor field-effect transistors (FETs), power dissipation has become a major challenge. Lowering down the sub-threshold swing (SS) is known as an effective technique to decrease the operating voltage of FETs and hence lower down the power consumption. However, the Boltzmann distribution of electrons (so-called ‘Boltzmann tyranny’) implements a physical limit to the SS value. Use of negative capacitance (NC) effect has enabled a new path to achieve a low SS below the Boltzmann limit (60 mV dec−1 at room temperature). In this work, we have demonstrated a NC-FET from an all two-dimensional (2D) metal ferroelectric semiconductor (MFS) vertical heterostructure: Graphene/CuInP2S6/MoS2. The negative capacitance from the ferroelectric CuInP2S6 has enabled the breaking of the ‘Boltzmann tyranny’. The heterostructure based device has shown steep slopes switching below 60 mV dec−1 (lowest to < 10 mV dec−1) over 3 orders of source-drain current, which provides an avenue for all 2D material based steep slope FETs.

Mechanisms of electrical conductivity, quantum capacity and negative capacitance effects in InSe nanohybrid

Mechanisms of electrical conductivity, quantum capacity and negative capacitance effects in InSe nanohybrid

Reduction of Random Dopant Fluctuation-induced Variation in Junctionless FinFETs via Negative Capacitance Effect

In this study, we investigated the impact of random dopant fluctuation (RDF) on junctionless (JL) fin field-effect transistors (FinFETs) with ferroelectric (FE) negative capacitance (NC) effect. The RDF-induced variations were captured by using built-in Sano methodology in three-dimensional technology computer-aided design (TCAD) simulation. Compared to the regular JL-FinFETs, the variations in JL-FinFETs with NC effect (NCJL-FinFETs) was observed to be less via statistical Monte Carlo analysis, which further enhanced its performance as well. The evaluation and estimation of threshold voltage (V T ), ON-state current (I on ), OFF-state current (I off ), and subthreshold swing (SS) by different FE layer thicknesses indicated reduction in the standard deviations of V T (δV T ) and I on (δI on ) by 34.7% and 7.08%, respectively; the OFF-state current and its standard deviation shrank by approximately three orders of magnitude than the JL-FinFET counterpart. Although δSS was not monotonous, the SS was significantly improved to sub-60 mV/decade. To sum up, the regular JL-FinFETs containing the FE layer as NC effect not only improved the electrical performance, but also led to the resilience of the RDF-induced statistical variability.

Performance analysis of nanowire and nanosheet NCFETs for future technology nodes

Negative capacitance (NC) effect in nanowire (NW) and nanosheet (NS) field effect transistors (FETs) provide the much-needed voltage scaling in future technology nodes. Here, we present a comparative analysis on the performance of NC-NWFETs and NC-NSFETs through fully calibrated, three-dimensional computer aided design (TCAD) simulations. In addition to single channel NC-NSFETs and NC-NWFETs, those, with vertically stacked NSs and NWs, have been examined for the same layout footprint (LF). Results show that NC-NSFETs can achieve lower subthreshold swing (SS) and higher ON-current (I ON ) than NC-NWFET of comparable device dimensions. However, NC-NWFETs show slightly higher I ON /I OFF ratio. Negative differential resistance (NDR) is found to be more pronounced in NC-NSFET, enabling these devices to attain a stronger drain-induced-barrier-rising (DIBR) and steeper SS for gate lengths as small as 10 nm. The results presented here can, therefore, provide useful insights for performance optimization of NC-NWFETs and NC-NSFETs, in ultra-scaled and high-density logic applications, for 7 nm and beyond technology nodes.

A Novel Negative Capacitance FinFET With Ferroelectric Spacer: Proposal and Investigation.

In this letter, for the first time, we investigate the role of Ferroelectric (FE) spacer in a negative capacitance (NC) FinFET. Using well-calibrated TCAD models, we found that instead of placing a dielectric (DE) spacer, if we use an FE spacer, enhanced electric field due to FE polarization can be achieved, thereby producing a higher ON-current. The fringing fields polarize the FE spacer and result in voltage amplification, which lowers the effective barrier and increases the current driving capability. ON-current of the proposed configuration, i.e., FE spacer at the source (S) side and DE spacer at the drain (D) side, is ~30% higher than the baseline FinFET. In this work, we have also proposed four different spacer placement configurations to realize better performances in terms of higher ON-current, mitigation of negative differential resistance (NDR) and better subthreshold slope (SS), and so on. We found that the optimized performance can be attained by placing an FE and DE spacer at the S and D end, respectively. We also evaluated a design space window for a good capacitance match to achieve NC effect for optimized device design.

Negative Capacitance Dual Electrode Junctionless TFET Based on Si Doped HfO 2 Ferroelectric Layer: Proposal and Optimization

This work reports negative capacitance dual electrode junctionless tunnel field effect transistor (NC-DE-JLTFET) based on Si doped HfO 2 ferroelectric (FE) layer as gate-stack. This FE layer is sandwiched between conventional gate dielectric layer and gate metal electrode. As the domains of FE get aligned due to polarization in the applied electric field directions it realizes intrinsic voltage amplification. This facilitates the smaller voltage swing in the gate voltage resulting in a larger swing in drive current. This enhances gate controlability, improves scalability, lowers threshold voltage and steepers sub-threshold slope (SS). However the most crucial designing aspect of negative capacitance (NC) based device is stabilizing the net capacitance of the structure otherwise it can cause system instability due to the NC behavior. In order to stabilize this NC effect here optimization of FE layer thickness has been carried out by parametric sweep optimization. The study reported minimum SS as 20 mV/dec with FE thickness of 2.5 nm. As JLTFET is a dopingless structure, source and drain side dielectric oxide thicknesses dictate the source and drain side induced doping, respectively. Hence the device performance estimation in terms of these thickness variations is also presented here in detail.

MoS2 negative-capacitance transistors with steep slope and negligible hysteresis by using monolayer Al1-xZrxOy as gate dielectric plus NH3-plasma treatment

Although ferroelectric material is highlighted for its negative capacitance (NC) effect integrated into MoS2 devices, it usually needs a dielectric layer to provide positive capacitance, which is not conducive to scaling down of transistors. In this work, a monolayer Al1-xZrxOy is used as the gate dielectric to fabricate back-gated MoS2 negative-capacitance FETs (NCFETs), in which host Al2O3 exhibits a positive capacitance and the embedded ZrO2 crystals formed through rapid thermal anneal at 550℃ exhibit a NC effect. By optimizing the Zr content in the Al1-xZrxOy thin film, an enhanced ferroelectricity and a reasonable match between the negative capacitance and the positive capacitance have been achieved for the Al0.93Zr0.07Oy thin film, resulting in excellent device performances: small subthreshold swing (SS) of 28 mV/dec and high on/off current ratio of 6.4 × 107. Moreover, after the Al0.93Zr0.07Oy thin film is suffered from a remote NH3-plasma treatment, its ferroelectricity and NC effect are further enhanced due to the reduction of oxygen vacancies and the improvement of interface quality, thus boosting the performance of the relevant NCFET: the SS is lowered to 18 mV/dec, where the sub-60 mV/dec SS spans almost three orders of Id (drain current) magnitude, the hysteresis is reduced to 25 mV and the driving current is 30% higher than that of the untreated sample. Therefore, the Al0.93Zr0.07Oy thin film with the NH3-plasma treatment as the gate dielectric of MoS2 NCFET has a great potential in achieving the steep-slope, free-hysteresis and low power-consumption performances.

Effect of Negative Capacitance in Partially Ground Plane based SELBOX FET on Capacitance Matching and SCEs

Here in, we investigated the impact of negative capacitance in PGP-SELBOX NCFET (partial ground plane on a selective buried oxide in negative capacitance FET) over FDSOI. The ferro-electric layer is placed in the gate stack of PGP-SELBOX NCFET to generate the negative capacitance phenomenon. Ferro-electric(FE) materials are similar to dielectric materials but differ in terms of their polarization properties. FE-HFO2 is used as ferroelectric material due to its sufficient polarization rate with high dielectric capacitance and better reliability. The effect of ferro-electric material parameters like coercive field(Ec) and remnant polarization(PR) on the capacitance matching of NCFET are analyzed. The simulation results reveal that the RPE factor, which is the ratio of PR to Ec, is closely related to better capacitance matching. In addition, the effect of variation in thickness of ferro-electric layer on the average sub-threshold swing(SS) is also explored. The relation between short channel effects (Vth rolloff and DIBL) and thickness of the ferro-electric (tfe) for PGP-SELBOX NCFET is also analyzed. The simulation results clearly show that PGP-SELBOX NCFET is having reduced SCEs and 103 times better \(\frac {\mathrm {I}_{\text {ON}}}{\mathrm {I}_{\text {OFF}}}\) ratio over FDSOI NCFET. For optimized value of ferro-electric parameters average SS for proposed device is found as 50 mV/decade at tfe = 5nm which is lesser than FDSOI NCFET (56 mV/decade).

Addressing source to drain tunneling in extremely scaled Si-transistors using negative capacitance

The impact of negative capacitance (NC) of the ferroelectric materials in controlling the direct source to drain tunneling (DSDT) in ultra-short channel FETs is presented in this paper. Besides, an analytical model is developed by solving 2-D Poisson’s equation incorporating the degeneracy of source/drain (S/D) regions. We demonstrate that in NC gate stack based Si channel FETs (NC-FETs), the scaling limit can be pushed down to 7 nm gate length, without using effective mass engineering and alternate channel materials. However, under severe subthreshold tunneling circumstances, we find that as the % content of tunneling current rises above the value of 50% in the net current, the subthreshold slope (SS) ceases to improve with the higher ferroelectric thickness. The rigorous analysis of DSDT-Negative drain induced barrier lowering (NDIBL) and impact of the S/D doping over DSDT is also incorporated in the paper. It is found that DSDT decreases drastically in the NCFET compared to baseline FETs due to the NC effect. Hence, using NC effect, transistor can be scaled down to 7 nm physical gate length with SS < 80 mV/dec and IOFF< 70 nA/μm compared to 173 mV/dec and 1.5×106 nA/μm, respectively for the baseline FET at the same gate length.

Sensitivity Analysis of a Novel Negative Capacitance FinFET for Label-Free Biosensing

We propose and analyze a dielectric modulated (DM) negative capacitance (NC) fin-field effect transistor (FinFET) based biosensor for efficient and label-free detection of biomolecular entities. For the first time, the NC effect on bio-sensing owing to the presence of a dielectric-ferroelectric gate oxide stack is investigated. First, capability of the NC-FinFET is compared with the baseline FinFET as percentage variation in electrical parameters. Also, the sensing capability of the proposed device is examined with a wide variety of biomolecules with varying dielectric constants. Inclusion of the NC effect in the biosensor exhibits very high sensitivity in terms of the electrical figures of merit (FoMs) such as threshold voltage, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm{\scriptscriptstyle ON}}/{I}_{\mathrm{\scriptscriptstyle OFF}}$ </tex-math></inline-formula> -ratio, output conductance, and intrinsic gain with rapid response because of the steep subthreshold value. The use of raised source drain (RSD) architecture allows more cavity space to the biomolecules and, hence, increases the sensitivity and selectivity of the biosensor. All the device simulations are performed in a 3-D Sentaurus TCAD environment using well-calibrated structure. To establish a benchmark, the sensitivity of the proposed biosensor is also compared with the published literature in order to determine its effectiveness. The results of this study can establish NC-FinFET as a viable candidate for label-free DM biosensor applications.

Recent Advances in Negative Capacitance FinFETs for Low-Power Applications: A Review.

In the contemporary era of Internet-of-Things (IoT), there is an extensive search for competent devices which can operate at ultralow voltage supply. Due to the restriction of power dissipation, a reduced sub-threshold swing-based device appears to be the perfect solution for efficient computation. To counteract this issue, negative capacitance fin field-effect transistors (NC-FinFETs) came up as the next-generation platform to withstand the aggressive scaling of transistors. The ease of fabrication, process-integration, higher current driving capability, and ability to tailor the short-channel effects (SCEs) are some of the potential advantages offered by NC-FinFETs that attracted the attention of researchers worldwide. The following review emphasizes how this new state-of-art technology supports the persistence of Moore's law and addresses the ultimate limitation of Boltzmann tyranny by offering a sub-threshold slope (SS) below 60 mV/decade. The article primarily focuses on two parts: 1) the theoretical background of negative capacitance (NC) effect and FinFET devices and 2) the recent progress done in the field of NC-FinFETs. It also highlights the crucial areas that need to be upgraded, to mitigate the challenges faced by this technology and the future prospects of such devices.

Polarization switching in Hf0.5Zr0.5O2-dielectric stack: The role of dielectric layer thickness

Understanding the role of the dielectric (DE) layer in ferroelectric (FE) Hf0.5Zr0.5O2 (HZO) based devices (e.g., ferroelectric-field-effect-transistors, FE-FETs) is important to enable their application-driven optimizations. To that end, in this work, we systematically investigate the polarization switching mechanisms in FE–DE stacks and analyze their dependence on the dielectric layer thickness (TDE). First, we fabricate a HZO–Al2O3 (FE–DE) stack and experimentally demonstrate a decrease in remanent polarization and an increase in coercive voltage with an increase in TDE. As such dependencies are out of the scope of commonly used single domain polarization switching models, therefore, we argue that the consideration of the multi-domain model is essential for analyzing the polarization switching in HZO. Then, using phase-field simulations of the FE–DE stack, we show that an increase in TDE results in a larger number of reverse domains in the FE layer to suppress the depolarization field, which leads to a decrease in the remanent polarization and an increase in the coercive voltage. Furthermore, our analysis signifies that the polarization switching mechanism in HZO can be modulated from domain-nucleation based to domain-wall motion based by increasing the TDE and that can serve as a potential knob for application-specific optimization of FE-FETs. In addition, we show that the effective polarization–voltage characteristics of the FE layer in the FE–DE stack exhibit a negative slope region that leads to the charge enhancement effects in the FE–DE stack. While such effects are most commonly misinterpreted as either the transient effects or the stabilized single-domain negative capacitance effects, we demonstrate that the appearance of a negative slope in the hysteretic polarization–voltage characteristics is quasi-static in nature and that originates from the multi-domain polarization switching in the FE.

MoS2 transistors gated by ferroelectric HfZrO2 with MoS2/mica heterojunction interface

Two-dimensional (2D) molybdenum disulfide (MoS2) field-effect transistor (FET) gated by negative capacitance (NC) is a promising architecture to overcome the thermionic limit and thus reduce device consumption. Here, top-gated MoS2 NCFETs have been prepared by transferring a mica flake on MoS2 channel to form a van der Waals heterojunction interface, together with a ferroelectric HfZrO2 (HZO) deposited on mica. Stable NC effects are demonstrated for MoS2 NCFETs. The MoS2 NCFETs integrated with mica/HZO gate stack provide competitive electrical characteristics when they are applied with a gate voltage sweep-width in the range of 1−3 V and a sweep-rate from 0.01 to 0.2 V s−1, including steep-slope of sub 60 mV dec−1 in four orders of magnitude of drain current, on/off current ratio over 106, and small hysteresis-width less than 50 mV. Outstanding performance should be ascribed to damage-free properties of mica/MoS2 van der Waals interface and capacitance matching between the HZO ferroelectric and mica dielectric. The results confirm the promising nature of mica/HZO gate stack and potential applications for future electronics.

Dual source negative capacitance GaSb/InGaAsSb/InAs heterostructure based vertical TFET with steep subthreshold swing and high on-off current ratio

Continuous downscaling of CMOS technology at the nanometer scale with conventional MOSFETs leads to short channel effects (SCE), increased subthreshold slope (SS), and leakage current, degrading the performance of ICs. We proposed a dual-source vertical tunnel field-effect transistor (TFET) with a steeper subthreshold swing (SS) and superior electrostatic control thanks to quantum mechanical band-to-band tunneling. We show that the use of GaSb/InGaAsSb/InAs heterostructure boosts the band-to-band tunneling rate in TFETs, resulting in higher on-state current. Incorporating the negative capacitance effect using ferroelectric materials further enhances the performance of the proposed device greatly. The lowest SS of 21.94 mV/dec and an on–off current ratio of 4.3267 × 1011 were obtained for dual source GaSb/InGaAsSb/InAs heterostructure based vertical TFET. The lowest subthreshold swing was found as 17.37 mV/dec after integrating Hf1–xZrxO2 ferroelectric material into the gate stack. The negative capacitance effect also increases the on-state current tenfold, resulting in an incredible ION/IOFF ratio of 1012. The suggested device focuses on low power consumption applications by assuring a very low leakage current and a reduced subthreshold swing.