Analysis of drain induced barrier lowering for junctionless double gate MOSFET using ferroelectric negative capacitance effect

Abstract

<abstract> <p>We analyze the drain induced barrier lowering (DIBL) of a negative capacitance (NC) FET using a gate structure such as a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) for a junctionless double gate (JLDG) FET. NC FETs show negative DIBL characteristics according to the ferroelectric thickness. To elucidate the cause of such negative DIBL, the DIBLs are obtained by the second derivative method using the 2D potential distribution and drain current-gate voltage curve. The analytical DIBL model is also presented for easy observation of the DIBL of NC FET. It has been found that the results of this analytical DIBL model are very similar to those of the second derivative method. The results of this analytical DIBL model are also in good agreement with the results of TCAD. As a result, it was found that the negative DIBL phenomenon is caused by the change according to the drain voltage of the charge existing in the ferroelectric material. The negative DIBL phenomenon easily occurred as the ferroelectric thickness increased and the thickness of SiO<sub>2</sub> used as an insulator decreases.</p> </abstract>