Abstract
In this work, we propose a negative-capacitance double-gate junctionless field-effect transistor (NC-JLFET) with additional source-drain doping for the first time. Superior performance of the NC-JLFET due to source and drain doping concentration is explained in detail. Additionally, the effects of the drain induced barrier lowering (DIBL) and negative differential resistance (NDR) are precisely analyzed in the NC-JLFET. Sentaurus TCAD simulation demonstrates that the additional source-drain-doped NC-JLFET exhibits a higher on/off current ratio ( I ON / I OFF ) and steeper subthreshold swing ( SS < 60 mV/dec) compared to a traditional JLFET. Besides, the negative capacitance effect causes the internal voltage of the gate to be amplified, resulting in negative DIBL and NDR phenomena. Finally, the performance of NC-JLFET can also be optimized by choosing suitable ferroelectric material parameters, such as ferroelectric thickness, coercive field, and remnant polarization. Our simulation study provides theoretical and experimental support for further performance improvement of low-power NCFETs by local structure adjustment.
Highlights
With the continuous development of integrated circuits (ICs), device sizes have been gradually shrinking
Using Sentaurus TCAD simulation, it is demonstrated that additional source-drain doped NC-junctionless FETs (JLFETs) have improved performance over traditional JLFETs, such as higher ION/ increases more and the off current (IOFF), steeper subthreshold swing (SS), and negative drain induced barrier lowering (DIBL)
The decrease of the barrier height allows the source electrons to cross the barrier to reach the drain, and the channel charge controlled by the gate voltage is reduced, which leads to increased leakage current and lowered threshold voltage
Summary
With the continuous development of integrated circuits (ICs), device sizes have been gradually shrinking. Zhao et al.; Informacije Midem, Vol 50, No 2(2020), 169 – 177 it has become difficult for inversion-mode field effect transistors (FETs) (IMFETs) to achieve ultra-deep doping concentration gradients at the device junctions, inducing increasing thermal budget [2]. To overcome these obstacles, some novel device structures have been proposed, including junctionless FETs (JLFETs) and ferroelectric negative-capacitance FETs (NCFETs) [3]-[5]. Using Sentaurus TCAD simulation, it is demonstrated that additional source-drain doped NC-JLFETs have improved performance over traditional JLFETs, such as higher ION/ IOFF, steeper SS, and negative DIBL
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