Abstract
This paper, based on the IRDS 2022 technology node, investigates the DIBL and short-channel effects for InGaAs negative-capacitance FinFETs (NC-FinFETs) through a theoretical subthreshold drain current model considering key effects including negative capacitance, quantum confinement and source-to-drain tunneling. Due to the impact of negative capacitance on the source-to-drain potential profile, tunneling distance and its drain-bias dependence, the short-channel effects can be substantially improved for InGaAs NC-FinFETs. Our study indicates that, with the larger NC effect of the III-V channel, the gap in DIBL and subthreshold swing between InGaAs and Si FinFETs in the sub-20 nm gate-length regime can become much closer. Our study may provide insights for future supply-voltage/power scaling of logic devices with high-mobility channel.
Highlights
Reducing the supply voltage (VDD) is crucial to power scaling of future CMOS
Ultra-thin-body InGaAs Negative-capacitance field-effect transistor (NCFET) has been experimentally reported [8], [9], and mitigation of the quantum-capacitance induced inversioncharge loss by the NC effect has been theoretically demonstrated for InGaAs NC-FinFET [10]
In this work, using a theoretical model corroborated with TCAD numerical simulation, we investigate and compare the short-channel effects including the DIBL for InGaAs and Si NC-FinFETs
Summary
Reducing the supply voltage (VDD) is crucial to power scaling of future CMOS. Negative-capacitance field-effect transistor (NCFET) [1]–[4] has been regarded as a promising beyond-CMOS device candidate due to its potential in improving subthreshold swing with similar current transport mechanism to MOSFET. III-V channel materials such as InGaAs are attractive (for nFET) because their high electron mobility can be used to sustain the drive current as VDD scales down [5]–[7]. In addition to the source-to-drain tunneling (SDT) current [11]–[15], the worsened drain-induced-barrier-lowering (DIBL) due to the higher channel permittivity of III-V devices is a problem for both the device electrostatic integrity and circuit performance [16]. While the gate-all-around device structure can be utilized to improve the electrostatic integrity of the transistor [6], [7], [17], whether the NC effect can mitigate these problems regarding SCEs and DIBL for scaled InGaAs devices is an important question and merits investigation
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