Abstract
Here in, we investigated the impact of negative capacitance in PGP-SELBOX NCFET (partial ground plane on a selective buried oxide in negative capacitance FET) over FDSOI. The ferro-electric layer is placed in the gate stack of PGP-SELBOX NCFET to generate the negative capacitance phenomenon. Ferro-electric(FE) materials are similar to dielectric materials but differ in terms of their polarization properties. FE-HFO2 is used as ferroelectric material due to its sufficient polarization rate with high dielectric capacitance and better reliability. The effect of ferro-electric material parameters like coercive field(Ec) and remnant polarization(PR) on the capacitance matching of NCFET are analyzed. The simulation results reveal that the RPE factor, which is the ratio of PR to Ec, is closely related to better capacitance matching. In addition, the effect of variation in thickness of ferro-electric layer on the average sub-threshold swing(SS) is also explored. The relation between short channel effects (Vth rolloff and DIBL) and thickness of the ferro-electric (tfe) for PGP-SELBOX NCFET is also analyzed. The simulation results clearly show that PGP-SELBOX NCFET is having reduced SCEs and 103 times better \(\frac {\mathrm {I}_{\text {ON}}}{\mathrm {I}_{\text {OFF}}}\) ratio over FDSOI NCFET. For optimized value of ferro-electric parameters average SS for proposed device is found as 50 mV/decade at tfe = 5nm which is lesser than FDSOI NCFET (56 mV/decade).
Highlights
In today’s era, demand for low power devices at nanoscale level is continuously increasing
Assessment of capacitance matching with variation in ferroelectric parameters Stabilizing the negative capacitance effect is a critical issue in capacitance matching among |Cfe|, Cmos and Cox [28]
|Cfe| ≈ > CMOS It can be seen that for negative-capacitance FETs (NCFETs) in order to function in negative capacitance region and to amplify VMOS to achieve high performance, the Cfe should be approximately equal or slightly greater than CMOS is a necessary condition
Summary
In today’s era, demand for low power devices at nanoscale level is continuously increasing. There is reduction in self heating during the achievement of high breakdown voltage Issues with such structure is that the magnitude of short channel effects is higher in these devices. To overcome the drawbacks of SELBOX structure, partial ground plane(PGP) is incorporated with SELBOX [17], due to which SCEs is reduced significantly This creates the scope of further scaling of the device. With PGP, coupling of electric field lines is minimized which results in reduction of short channel effects like DIBL, SS,Vth roll off.
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