Role of Interfacial Oxide on Capacitance Matching in a Negative Capacitance FinFET: A Reliability Perspective

Abstract

Capacitance matching is a prime requirement to realize a Negative Capacitance (NC) FET. The ferroelectric (FE) layer in the gate stack with an interfacial oxide (IO) put forward two capacitances in series, resulting in internal voltage amplification when/if capacitance matching occurs. In recent NCFETs, we take doped-HfO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> as a FE layer and SiO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> as a conventional IO layer. However, different IO layers might offer different capacitances and thus require proper capacitance matching tuning. In this paper, using well-calibrated TCAD models, we realized a 14nm NC-FinFET and investigated the (i) impact of placing different IO layers on capacitance matching by keeping similar effective oxide thickness (EOT) and FE-layer (i.e., Si-doped HfO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> ) (ii) the overall impact of different IO layers on current ratio, subthreshold slope (SS), threshold voltage and analog metrics, such as gate capacitance, transconductance, output resistance, intrinsic gain, etc. (iii) impact of tuning the gate metal work-function on device characteristics. Thus, the proposed analysis is worth exploring as it provides the design guidelines for a reliable NC-FinFET operation.