Negative Capacitance Dual Electrode Junctionless TFET Based on Si Doped HfO 2 Ferroelectric Layer: Proposal and Optimization

Abstract

This work reports negative capacitance dual electrode junctionless tunnel field effect transistor (NC-DE-JLTFET) based on Si doped HfO 2 ferroelectric (FE) layer as gate-stack. This FE layer is sandwiched between conventional gate dielectric layer and gate metal electrode. As the domains of FE get aligned due to polarization in the applied electric field directions it realizes intrinsic voltage amplification. This facilitates the smaller voltage swing in the gate voltage resulting in a larger swing in drive current. This enhances gate controlability, improves scalability, lowers threshold voltage and steepers sub-threshold slope (SS). However the most crucial designing aspect of negative capacitance (NC) based device is stabilizing the net capacitance of the structure otherwise it can cause system instability due to the NC behavior. In order to stabilize this NC effect here optimization of FE layer thickness has been carried out by parametric sweep optimization. The study reported minimum SS as 20 mV/dec with FE thickness of 2.5 nm. As JLTFET is a dopingless structure, source and drain side dielectric oxide thicknesses dictate the source and drain side induced doping, respectively. Hence the device performance estimation in terms of these thickness variations is also presented here in detail.