Double-gate FinFET Research Articles

Design Equivalent Scaling on Double Gate FinFET Towards Analog and RF Figures of Merits: A Technology Computer Aided Design Estimation

Design Equivalent Scaling on Double Gate FinFET Towards Analog and RF Figures of Merits: A Technology Computer Aided Design Estimation

Impacts of Trapezoidal Fin of 20-nm Double-Gate FinFET on the Electrical Characteristics of Circuits

In this study, we analyze the impacts of the trapezoidal fin shape of a double-gate FinFET on the electrical characteristics of circuits. The trapezoidal nature of a fin body is generated by varying the angle of the sidewall of the FinFET. A technology computeraided-design (TCAD) simulation shows that the onstate current increases, and the capacitance becomes larger, as the bottom fin width increases. Several circuit performance metrics for both digital and analog circuits, such as the fan-out 4 (FO4) delay, ring oscillator (RO) frequency, and cut-off frequency, are evaluated with mixed-mode simulations using the 3D TCAD tool. The trapezoidal nature of the FinFET results in different effects on the driving current and gate capacitance. As a result, the propagation delay of an inverter decreases as the angle increases because of the higher on-current, and the FO4 speed and RO frequency increase as the angle increases but decrease for wider angles because of the higher impact on the capacitance rather than the driving strength. Finally, the simulation reveals that the trapezoidal angle range from 10° to 20° is a good tradeoff between larger on-current and higher capacitance for an optimum trapezoidal FinFET shape.

Impact of Varying Fin Width in an n-FinFET at 20nm Gate Length

double gate FinFET can reduce drain induced barrier lowering and improve threshold (short channel effects). In this paper, a very important geometrical parameter, that is, the fin width of a FinFET has been analyzed. In this article, a double gate n channel FinFET with a gate length of 20nm has been reported. The transfer characteristics of the FinFET at various fin widths have been obtained at a supply voltage of 0.1 V. A comparison is then made between the transfer characteristics of various fin widths. It is observed that, at greater fin widths the drain current also increases as compared to that at shorter fin widths. Thus an increase in device performance is expected, but at the cost of increase in short channel effects. All the simulations have been performed in visual TCAD (Tiber CAD).

Spice modeling of oxide and interface trapped charge effects in fully-depleted double-gate FinFETs

As is the case with conventional planar MOS transistors, the electrical characteristics of highly-scaled multi-gate field-effect transistors (FinFETs) also suffer from temporal degradations occurring due to hot-carrier injection, bias temperature instability and/or ionizing-radiation damage. The FinFETs aging is caused by cumulative contribution of the generation of oxide/Si interface traps and positively charged defects within the gate oxide. The accurate capturing of the dynamic contribution of the both trapped charges by the FinFET electrical models in Spice simulations is important for lifetime prediction and verification of long-term performance of advanced CMOS ICs. In this paper, the auxiliary sub-circuit is described aimed for including the effects of oxide and interface trapped charges in Spice electrical models of fully-depleted double-gate FinFETs. The efficiency of the proposed sub-circuit for modeling the aging effects in double-gate FinFETs is verified using two-dimensional TCAD device simulations.

(Plenary) Physical Insights on the Design of UTB Devices, Including FinFETs

A revolution in device design for nanoscale CMOS is now occurring because the conventional bulk-Si MOSFET can no longer be scaled due to channel-doping limitations. Two novel devices with undoped ultra-thin bodies (UTBs), the quasi-planar FinFET, on bulk Si or SOI, and the planar fully depleted (FD) SOI MOSFET, are now the prime candidates for nanoscale CMOS. This paper, based on our recently published textbook on UTB devices [1], overviews the unique physics of these new CMOS devices, and offers insights on their designs, scalabilities, and performance potentials. The characterization of the threshold voltage of the FinFET and the FD-SOI MOSFET is unique and generally complex, but generic, following from the application of Poisson's Equation and Gauss's Law in the undoped UTB. It simplifies for the long symmetrical double-gate (DG) FinFET (Vt ≈ ΦMSf + φc where φc ≈ 0.4V is the surface potential at the threshold condition), and, for the FD-SOI MOSFET, yields Vt(VGbS, ΦMSb) which shows how Vt can be varied via substrate bias and/or doping. Also, Vt is increased by energy quantization, dependent on UTB thickness (tSi, with tSi < 4nm being prohibitive) and transverse electric field, and it is decreased by short-channel effects (SCEs), dependent strongly on tSi. Regarding SCE control, the DG FinFET is superior to the FD-SOI MOSFET which requires substantially thinner tSi. The triple-gate (TG, with a fin-top gate) device is not much better than the DG device in this regard, nor does it offer much Ion improvement due to the prevalent bulk inversion in the undoped UTB. The SCE control is dramatically improved by a gate-source/drain underlap, defined by the source/drain lateral doping profile, that implies an effective channel length (Leff) longer than the gate length (Lg) for weak inversion, but Leff ≈ Lgfor strong inversion. Such optimal design is peculiar to undoped channels. The superior SCE control with FinFETs implies better scalability, and Intel Corp. has chosen [2] this device for its nanoscale CMOS. For vague reasons, it chose bulk Si for the substrate as opposed to SOI. Nonetheless, it appears that SOI will ultimately be needed (for Lg → <10nm), mainly because of unavoidable random variations in the high doping (PTS) density needed at the base of the fin to stop drain-source punch-through leakage. This leakage current is examined, in terms of the PTS doping density (~1018cm-3 is optimal), and variations in Vt and Iondue to the random PTS variations clearly imply problems in nanoscale bulk-Si FinFETs. Further, the PTS variations can undermine the control of the G-S/D underlap. The examination of the bulk-Si vs. SOI FinFET issue is concluded by noting a processing issue for FinFETs on SOI wafers, and suggesting that a local-SOI structure in bulk Si could be the ultimate solution. The physical insights overviewed herein imply a set of pragmatic FinFET design criteria that, we believe, can simplify the technology without undermining the CMOS performance much. They include the following: use an SOI structure (e.g., local in bulk Si); use an undoped UTB/channel with tSi > 4nm; use DG as opposed to TG; use no high-k dielectric (as implied by effects of strong bulk inversion); use one ~midgap metal gate for LP, and perhaps dual gates for HP; use optimal G-S/D underlap; use no channel strain (carrier mobilities can be high without it); and possibly use optimal S/D processing for Vtcontrol (and underlap). SRAM simulations demonstrate the viability of such pragmatic FinFET design.

Geometrical Magnetoresistance in Multi-Gate FDSOI Structures

Mobility characterization is very challenging on SOI multi-gate transistors where several channels coexist and interact [1-3]. Among all mobility determination procedures, only the geometrical magnetoresistance yields accurate values free of any assumption (channel length, oxide and film thickness, doping, strain, etc). Magnetoresistance is a direct consequence of carrier deflection by a magnetic field. When carriers do not follow the shortest path from source to drain, the channel resistance increases. The relation between the resistances obtained when the magnetic field is present or not yields: RB = R0 ( 1 + μMR 2 B2 ) The carrier deviation by the Lorentz force is shown in Fig. 1a. The deviation is modulated by the device geometry. If the transistor is long and narrow (W/L < 1) the Hall field opposes to the Lorentz force and the magnetoresistance is weak. However, when the sample is wide and short (W/L >> 1) the Hall field is short-circuited by the end contacts and the Lorentz force is not compensated. Hence, carriers are deviated and the magnetoresistance is maximum. Fig. 2 illustrates the simulated electron mobility against the aspect ratio (W/L) for several magnetic field orientations. The magnetoresistance is much higher for normal magnetic fields (and W/L > 5) than for transversal fields as fully documented by experimental data [4]. On the other hand, in double-gate FinFETs (Fig. 1b), the magnetoresistance is high even in narrow samples (W ~ L). This surprising result was explained by the lateral gate action which cancels the Hall voltage so preventing the compensation of the Lorentz force and resulting in the magnetoresistance [4]. TCAD numerical simulations [5] were carried out to clarify the carrier deflection and magnetoresistance mobility in FinFETs. The impact of the device architecture, thicknesses, gate biasing scheme, and magnetic field orientation is documented and explained.

The impact of process variations on input impedance and mitigation using a circuit technique in FinFET-based LNA**Project supported by the Defense Research Development Organization (DRDO), Government of India.

The effect of process variations of a FinFET-based low noise amplifier (LNA) are mitigated by using the device in an independently driven mode, i.e. an independently driven double gate (IDDG) FinFET. A 45 nm gate length IDDG FinFET-based cascoded LNA, operating at 5 GHz, is designed and studied to assess the impact of process variation on the LNA performance metrics such as input impedance, gain and noise figure. Four geometrical parameters, gate length, channel width, gate oxide thickness and fin width, and one non-geometrical parameter, channel doping concentration, are considered in the study. The effect of these variations on the input impedance (the desired value is 50 Ω purely real) of the LNA is compensated by the second gate bias of the IDDG FinFET.

IJARCCE - Computer and Communication Engineering

In this paper, a low power independent-gate, process variation tolerant double gate (DG) Fin FET based sense amplifier design has been proposed. As like RHIGSA, new design exploits the DICE (dual interlock cell) latch and the back gate of a double-gate Fin FET (DG Fin FET) device for dynamic compensation against process variation. But, there is change in tail transistor gate connections.,Which is dynamically controlled by intermediate signal in circuit. This design improves the power dissipation and show excellent tolerance to process parameter variations like temperature, Vdd, thickness of oxide compared to Radiation hardend IGSA (RHIGSA) circuit and independent gate sense amplifier (IGSA). Proposed technique consumes 29.108% less power compare to RHIGSA.

Impact of Fin Width and Back Bias Under Hot Carrier Injection on Double-Gate FinFETs

This study compares the effects of n-channel double-gate FinFETs with fin widths $(W_{\rm fin} ) $ of 10 and 25 nm with those of such devices with back biases and hot carrier injection (HCI. Compared with the device with a wide $W_{\rm fin}$ , the device with a narrow $W_{\rm fin} $ exhibits a larger current tuning range but a more off-state current leakage at a positive back bias because of the forward-biased p-n junction and the higher degradation under HCI. The gate-induced drain leakage significantly deteriorates with a positive back bias after HCI because of the generation of interfacial charges. However, a negative back bias causing hot hole injection during HCI can alleviate the degradation compared with unbiased and positive-biased devices.

New Topology Approach for Future Process, Voltage and Temperature Aware SRAM Using Independently Controlled Double-Gate FinFET

New Topology Approach for Future Process, Voltage and Temperature Aware SRAM Using Independently Controlled Double-Gate FinFET

Influence of gate engineering on the optical characteristics of a double gate FinFET

In this paper, the potential benefit of short channel triple material double gate (TM-DG) FinFET on the optical performance characteristics considering quantum mechanical effects has been theoretically examined and analyzed. The device characteristics are obtained from the self-consistent solution of 3D Poisson–Schrödinger equation using Leibmann's iteration method and provided the reasons for improved performance. The drain and transfer characteristics, electric field, transconductance and mobility of the device have been estimated and the results were compared with the device simulator results. The effect of different length ratios of three channel regions related to three different materials of TM-DG FinFET structure on the optical characteristics have also been discussed. The model is purely a physics based one and overcomes the major limitations of the existing 2D/3D analytical models by providing a more accurate result. The results obtained for dark and illuminated conditions are used to examine the performance of the device for its suitable use as a photodetector.

Enhanced coupling effects in vertical double-gate FinFETs

Vertical double-gate (DG) FinFETs fabricated on SOI wafers show good gate control, reasonable threshold voltage and high carrier mobility despite the absence of the top-gate. The 3D coupling effect between the two lateral-gates and the back-gate is investigated based on experimental and simulation results. We compare DG and triple-gate FinFETs with various fin widths. Front-channel characteristics are easily tuned by applied bias at the back-gate if the fin is not too narrow. We highlight that vertical DG FinFET is more appropriate device for dynamic threshold voltage adjustment than triple-gate FinFET. An analytical model is proposed to quantify the coupling effect in DG FinFET by solving 2D Poisson equation. The body potential profile and coupling effect are modeled. A very good agreement is obtained between experiments, 3D simulations and the proposed model.

3D Simulation of Fin Geometry influence on Corner effect in Multifin Dual and Tri-gate SOI-FinFETs

In this work the corner effect sensitivity to fin geometry variation in multifin dual and tri-gate SOI-FinFETs is studied through a commercial, three-dimensional numerical simulator ATLAS from Silvaco International. These devices are compatible with conventional silicon integrated circuit processing, but offer superior performance as the device is scaled into the nanometer range. This study aims wider to use multiple fins between the source and drain regions. The results indicate that for both multifin double and triple gate FinFETs, the corner effect does not lead to an additional leakage current and therefore does not deteriorate the SOI-FinFET performance. DOI : http://dx.doi.org/10.11591/telkomnika.v12i4.4668

Investigation of Tunable Characteristics of Independently Driven Double Gate FinFETs in Analog/RF Domain Using TCAD Simulations

“Modulating the front gate response of independently driven double gate (IDDG) FETs by the application of a control voltage on the second gate” is elaborately studied in this work using TCAD simulations and shown as a simple and powerful technique to tune the RF characteristics of the IDDG device. The input impedance, ft, and noise figure (NF) of the device can be modulated (tuned) by varying the control voltage applied to the gate2 of the IDDG device. Control gate bias values of 0Vt o+0� 4 V gives a wide tuning range for real part and imaginary part of the input impedance. NQS delay can be tuned in a better manner for low values of the control gate voltage (−0� 4Vt o 0 V). Signal gate voltages of 0.4 V to 0.5 V and control gate voltages of around −0� 1Vt o+0� 1V gives the optimum noise performance.

Analysis of Conventional CMOS and FinFET based 6-T XOR-XNOR Circuit at 45nm Technology

technology has scaled down, the implications of leakage current and power analysis for memory design have increased. To minimize the short channel effect Double-gate FinFET can be used in place of conventional MOSFET circuits due to the self-alignment of the two gates. Design for XOR and XNOR circuits is suggested to improve the speed and power. These circuits act as basic building blocks for many arithmetic circuits. This paper contrasts and evaluates the performance of conventional CMOS and FinFET based XOR-XNOR circuit design. It is based on the study of high speed, low power, and small area in XOR-XNOR digital circuits. The proposed FinFET based XOR and XNOR circuits have been designed using Cadence VIRTUOSO Tool applying voltage supply of 0.2 to 1.2 voltages, with temperature at 27 0 C and all the simulation results have been generated by Cadence SPECTRE simulator at 45nm technology. Simulation results exhibit low power, delay, power, delay product (PDP), and average dynamic power consumption.

Effects of Fin Width on Device Performance and Reliability of Double-Gate n-Type FinFETs

This paper investigates the impact of fin width ( W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fin</sub> s = 15, 20, and 25 nm) in a double-gate n-type FinFET on the performance and reliability of the device. Carrier conduction in the Si-fin body of FinFETs with various W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fin</sub> s is also studied. The experimental results show that the threshold voltage and drain current of n-type FinFETs increases and decreases, respectively, as W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fin</sub> is reduced. A thinner W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fin</sub> FinFET exhibits greater immunity to short channel effects. In addition, according to the analysis results of low-frequency noise, the thinnest W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fin</sub> FinFET possesses the largest bulk oxide trap density (N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BOT</sub> ) than that of a thicker W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fin</sub> FinFET. Moreover, the noise of the thinnest W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fin</sub> (15 nm) FinFET is largely dominated by the fluctuation of carrier number. In the hot-carrier injection (HCI) reliability test, the thinnest W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fin</sub> FinFET shows less performance degradation than those of the thicker ones. However, by removing the effect of the parasitic source/drain resistance, we believe that the volume inversion charged carriers flow through the entire thin Si-fin having a lower surface roughness and Coulomb scattering than those of thicker ones, which results in a higher carrier temperature and worsening of the reliability of the HCI.

Analysis of Leakage Reduction Techniques in Independent-Gate DG FinFET SRAM Cell

Scaling of devices in bulk CMOS technology leads to short-channel effects and increase in leakage. Static random access memory (SRAM) is expected to occupy 90% of the area of SoC. Since leakage becomes the major factor in SRAM cell, it is implemented using FinFET. Further, double-gate FinFET devices became a better choice for deep submicron technologies. With this consideration in our research work, 6T SRAM cell is implemented using independent-gate DG FinFET in which both the opposite sides of gates are controlled independently which provides better scalability to the SRAM cell. The device is implemented using different leakage reduction techniques such as gated-Vdd technique and multithreshold voltage technique to reduce leakage. Therefore, power consumption in the SRAM cell is reduced and provides better performance. Independent-gate FinFET SRAM cell using various leakage reduction techniques has been simulated using Cadence virtuoso tool in 45 nm technology.

A replacement of high-k process for CMOS transistor by atomic layer deposition

A replacement of high-k process was implemented on an independent double gate FinFET, following the ordinary gate-first process with minor modifications. The present scheme involves neither exotic materials nor unprecedented processing. After the source/drain process, the sacrificial gate oxide was selectively substituted with amorphous Ta2O5 via conformal plasma enhanced atomic layer deposition. The present gate-first gate-dielectric-last scheme combines the advantages of the process and design simplicity of the gate-first approach and the control of the effective gate workfunction and the interfacial oxide of the gate-dielectric-last approach. Electrical characterization data and cross-sectional images are provided as evidence of the concept.

Effect of underlap and soft error performance in 30 nm FinFET-based 6T-SRAM cells with simultaneous and independent driven gates

The effect of Gate-Source/Drain underlap (L un) on soft error performance in 30 nm common double gate-FinFET (simultaneously driven gates) and independent double gate-FinFET (independently driven gates) have been examined through extensive mixed mode-device and circuit simulations using Sentaurus TCAD. Four different 6T-SRAM topologies, one simultaneously driven double gate-FinFET and three independently driven double gate-FinFETs-based topologies namely Flex-V TH, Flex-PG, and PG-SN are chosen to study the geometrical parameter L un and also to calculate their soft error performance. When L un increases, current decreases due to increase in parasitic series resistance. The simulation results reveal that L un increase in independently driven double gate-FinFETs in place of access devices in 6T-SRAM does not degrade the soft error performance significantly whereas the L un increase inside the cell, in the inverters, degrade the performance significantly.

(Invited) Electrical Characterization and Reliability Assessment of Double-Gate FinFETs

The performance and reliability of doped and undoped (100)<100> and (110)<110> sidewall silicon-on-insulator (SOI) FinFETs with an Hf-based gate dielectric were evaluated. The electron mobility of the (110) FinFET sidewall is comparable to the (100) FinFET sidewall devices, which is opposite of the typical planar MOSFET electron mobility dependence on orientation, wherein (110) degrades significantly. In addition, TiN metal gate-induced strain cannot completely explain the similarity in (110) and (100) electron mobility because, although lower in magnitude, the two orientations with polysilicon electrodes resulted in similar mobility values. When investigating the orientation dependence of negative bias temperature instability (NBTI), (110) was found to cause more degradation than (100), and FinFETs with higher fin body doping demonstrated even more degradation.