Design of 0.8V, 22 nm DG-FinFET based efficient VLSI multiplexers

Abstract

Conventional CMOS has become successful logic for most digital VLSI circuits and a good candidate in terms of power dissipation. But due to its dual nature, more transistors are required and are not suitable as the technology is scaled down. This paper proposes a Double Gate (DG) FinFET based 4-1, 8-1, 16-1 multiplexer (DFMs) with a reduced number of transistors catering to the needs of low-power dissipation and high speed. For designing the proposed 4-1 DG-FinFET digital multiplexer (DFM) circuit requires only 16 FinFETs. Compared to the CMOS multiplexer circuit's conventional architecture, the proposed 4-1 DFM design uses a single pull-up FinFET in its first stage, and the second stage has only 4 FinFETs. The DFM circuit design is extended to 8-1 and 16-1 targeting to reduce transistor count, delay, and power dissipation. Extensive simulations are done at a 22 nm technology node using Eldo software of Mentor Graphics. With the simulated results of proposed and conventional CMOS designs at different supply voltages and load capacitances on the 22 nm technology node, the proposed DFM multiplexers' power-delay product is better. For 1 GHz of frequency and the least feasible supply voltage of 0.8 V, the proposed digital multiplexer attains a 10% reduction in power dissipation and a 6% reduction in delay. Including inverters in the designs, the transistor count is also less compared to the conventional static multiplexer.