Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor Reordering

S M Rezaul Hasan,Yufridin Wahab

doi:10.1080/1065514021000012165

S M Rezaul Hasan, Yufridin Wahab

Open Access

https://doi.org/10.1080/1065514021000012165

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Journal: VLSI Design	Publication Date: Jan 1, 2002
Citations: 6	License type: CC BY 3.0

Affiliation: University of Sharjah, Sirim Berhad

Abstract

This paper explores the deterministic transistor reordering in low-voltage dynamic BiCMOS logic gates, for reducing the dynamic power dissipation. The constraints of load driving (discharging) capability and NPN turn-on delay for MOSFET reordered structures has been carefully considered. Simulations shows significant reduction in the dynamic power dissipation for the transistor reordered BiCMOS structures. The power-delay product figure-of-merit is found to be significantly enhanced without any associated silicon-area penalty. In order to experimentally verify the reduction in power dissipation, original and reordered structures were fabricated using the MOSIS 2 μm N-well analog CMOS process which has a P-base layer for bipolar NPN option. Measured results shows a 20% reduction in the power dissipation for the transistor reordered structure, which is in close agreement with the simulation.

Highlights

Reordering of elements/primitives in a set/structure is an well-known characteristic in the inner works of nature
A reduction in the power dissipation by around 20% has been achieved through the transistor reordering
Simulation and experimental verification of the performance enhancement of dynamic BiCMOS logic gates through a novel deterministic transistor reordering technique has been provided

Summary

INTRODUCTION

Reordering (or permutation) of elements/primitives in a set/structure is an well-known characteristic in the inner works of nature. In a typical dynamic BiCMOS logic gate (the Kuo structure in Fig. 1(a)) reordering the position of the METER in the PMOS logic input chain (varying the separation from the VDD rail) may result in multiple threshold voltage (VTH) ranges for the METER. This is due to the gradation in the backgate reverse bias as shown in Fig. 2(b)assuming that the body (the substrate) is tied to the VDD rail (e.g. in a P-well process technology). The gate-to-source voltage of the METER, VGSMETERðtÞ 1⁄4 ðVn1ðtÞ 2 VDDÞ will reach VTHP (turn-off point) of the METER earlier for FIGURE 3 Transistor reordering to reduce charge redistribution: (a) the original circuit, and (b) the transistor reordered circuit

SIMULATION RESULTS

EXPERIMENTAL RESULTS

CONCLUSION