Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor Reordering

Abstract

This paper explores the deterministic transistor reordering in low‐voltage dynamic BiCMOS logic gates, for reducing the dynamic power dissipation. The constraints of load driving (discharging) capability and NPN turn‐on delay for MOSFET reordered structures has been carefully considered. Simulations shows significant reduction in the dynamic power dissipation for the transistor reordered BiCMOS structures. The power‐delay product figure‐of‐merit is found to be significantly enhanced without any associated silicon‐area penalty. In order to experimentally verify the reduction in power dissipation, original and reordered structures were fabricated using the MOSIS 2 μm N‐well analog CMOS process which has a P‐base layer for bipolar NPN option. Measured results shows a 20% reduction in the power dissipation for the transistor reordered structure, which is in close agreement with the simulation.