Abstract
Timing optimization for logic circuits is one of the key steps in logic synthesis. Extant research data are mainly proposed based on various intelligence algorithms. Hence, they are neither comparable with timing optimization data collected by the mainstream electronic design automation (EDA) tool nor able to verify the superiority of intelligence algorithms to the EDA tool in terms of optimization ability. To address these shortcomings, a novel verification method is proposed in this study. First, a discrete particle swarm optimization (DPSO) algorithm was applied to optimize the timing of the mixed polarity Reed-Muller (MPRM) logic circuit. Second, the Design Compiler (DC) algorithm was used to optimize the timing of the same MPRM logic circuit through special settings and constraints. Finally, the timing optimization results of the two algorithms were compared based on MCNC benchmark circuits. The timing optimization results obtained using DPSO are compared with those obtained from DC, and DPSO demonstrates an average reduction of 9.7% in the timing delays of critical paths for a number of MCNC benchmark circuits. The proposed verification method directly ascertains whether the intelligence algorithm has a better timing optimization ability than DC.
Highlights
Timing optimization for logic circuits is one of the most important requirements during logic synthesis [1,2,3,4]
To verify that an intelligence algorithm is better than the Design Compiler (DC) algorithm in the timing optimization of mixed polarity Reed-Muller (MPRM) logic circuits, a novel verification method was proposed in this study
The discrete particle swarm optimization (DPSO) algorithm was used to optimize the timing of the MPRM logic circuits
Summary
Timing optimization for logic circuits is one of the most important requirements during logic synthesis [1,2,3,4]. As shown by the red line, a typical path, denoted as the critical path, for the process of timing optimization in DC begins from the clock pin of FF1, passes through logic circuits, and arrives at the D pin of FF2. Logic circuits with n inputs and m outputs are transformed to equivalent mixed polarity Reed-Muller (MPRM) [9, 10] circuits, which have. The experimental results of intelligence algorithms cannot be compared with those of mainstream EDA tools, making the verification of the superiority of intelligence algorithms over EDA tools impossible. To address these problems, this research proposed a new related verification method. The suggested verification method allows for contrast analysis between the experimental results of an intelligence algorithm and the optimization outcomes of an EDA tool, thereby evaluating the optimization ability of the intelligence algorithm
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