A Novel Low Power and Reduced Transistor Count Magnetic Arithmetic Logic Unit Using Hybrid STT-MTJ/CMOS Circuit

Prashanth Barla,Somashekara Bhat,Vinod Kumar Joshi

doi:10.1109/access.2019.2963727

Prashanth Barla, Somashekara Bhat + Show 1 more

Open Access

https://doi.org/10.1109/access.2019.2963727

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Journal: IEEE Access	Publication Date: Jan 1, 2020
Citations: 72	License type: CC BY 4.0

Affiliation: Manipal Academy of Higher Education

Abstract

One of the major concern for CMOS technology is the increase in power dissipation as the technology node lowers down to deep submicron region. Magnetic tunnel junction (MTJ) working on Spin transfer torque (STT) switching mechanism is recognized as one of the most promising spintronic device for post CMOS era due to its non-volatility, high speed, high endurance, CMOS compatibility and mainly the low power dissipation which can offer the solutions for the problems posed by existing CMOS technology. We have proposed a novel logic-in-memory (LIM) architecture of magnetic arithmetic logic unit (P-MALU) based on hybrid STT-MTJ/CMOS circuits. Simulation results reveal that there is significant reduction in the total power dissipation and transistor count of arithmetic unit by 28.44% and 29.16% compared to double pass transistor logic based clocked CMOS ALU design (DPTL-C 2 MOS-ALU), while 58.87% and 45.16% to modified magnetic arithmetic logic unit (M-MALU) respectively. Reduction in average power dissipation for logical unit is 37.61% and 52.55% along with 47.22% and 42.42% fewer transistors than DPTL-C 2 MOS-ALU and M-MALU design respectively. Monte-Carlo(MC) simulation is then performed by incorporating process and mismatch variations for CMOS and extracted parameters of MTJ, to study the behavior of DPTL-C 2 MOS-ALU, M-MALU and P-MALU designs in terms of power dissipation. All the simulation results reveal that the P-MALU is superior than other two ALU designs in terms of power dissipation, delay and device count. Further, the P-MALU circuit is extended for 4-bits arithmetic operations. Electrical simulations are performed to verify the functionality of the design for higher bit operations which demonstrates the feasibility of the proposed design in VLSI circuits.

Highlights

In this modern era of information and technology, high performance portable electronic devices are ubiquitous
When the magnetic orientation of the free layer and fixed layer are in the same direction, the resistance offered by the device for the flow of current is less, and that state is denoted by RP, whereas, if the magnetic orientation of free layer is opposite to the fixed layer, the device offers higher resistance to the flow of read current and it is in the high resistance state RAP
To design the arithmetic unit of DPTL-C2MOS-Arithmetic logic unit (ALU), we have used the CMOS conventional 1-bit full adder obtained from standard cell library of STMicroelectronics design kit [45], [46] and is shown in Appendix

Summary

INTRODUCTION

In this modern era of information and technology, high performance portable electronic devices are ubiquitous. P. Barla et al.: Novel Low Power and Reduced Transistor Count Magnetic Arithmetic Logic Unit Using Hybrid STT-MTJ/CMOS Circuit their barrier thickness so that they are fully compatible with the present CMOS technology [6], [7]. Guo et al [43] proposed novel architecture of magnetic arithmetic logic unit (MALU) using hybrid STT-MTJ/CMOS structure. In our initial step to design magnetic ALU using logic-in-memory (LIM) structure, we developed 1-bit MALU which can be obtained by modifying the original structure of 1-bit MALU design reported by Guo et al [43] We named this structure as modified magnetic arithmetic logic unit (M-MALU) throughout the manuscript. Encouraged by the results obtained by [9], we have proposed a novel magnetic arithmetic logic unit (P-MALU) based on LIM architecture using hybrid STT-MTJ/CMOS circuits. Appendix representing the structure of 1-bit DPTL-C2MOS-ALU adder circuit has been appended for convenience

BACKGROUND

MTJ SWITCHING MECHANISM

RESULTS AND DISCUSSION

CONCLUSION