Optimization of Power and Delay in VLSI Circuits using Hybrid Flip-Flop Circuit

Abstract

In this paper a novel master-slave (MS) hybrid flip-flop is proposed using a single-phase clock.The proposed circuit is designed in CMOS (Complementary Metal Oxide Semiconductor) at 45-nm.Proposed structure is designed with low complexity level. In proposed flip flop circuit (PFC) width of the transistor is increased at the output stage, thus it minimizes the delay and increasing the efficiency of the circuit.In terms of power dissipation,the PFC has minimized by 47.24%,there is a reduction of delay 0.6 times lower as compared to hybrid flip flop (HFF).Moreover power delay product (PDP) is minimized to 49.11% compared to HFF.The results are verified using Monte carlo analysis.Consequently PFC improves power dissipation,PDP and delay as compared to existing circuit. Furthermore, It can operate up to 1 GHz frequency.