Design of a D flip flop for optimization of power dissipation using GDI technique

Abstract

It is aimed to present the methodology used for of optimization of power consumed by a D flip flop using gate diffusion input technique using the gate clocking methodology. A further 1.38% optimization is obtained by using this method, of the already optimized GDI D flip flop circuit using D flip flop triggered on single edge of clock. The Gate diffusion technique is used after analyzing a number of D flip flop circuits since it is found to give the lowest power delay product as compared to other CMOS configurations.