Abstract
A floating point multiplier (FPM) is one of the building block for various appliances such as arithmetic logic unit (ALU), digital signal processor (DSP), and computational dynamic range applications. The most usable standard to represent FPM is Institute of Electrical and Electronics Engineers (IEEE)—754, which segregated into three fields—Sign, exponent and mantissa field. The operation of FPM consists three stages—pre-normalization, multiplication, and post-normalization process. The normalization process is utmost important progress for any floating point computations. Thus, this paper deals with post-normalization process of 32-bit and 64-bit FPM by using intermediate product (IP) shifter design, which shifts 1-bit operand to right side. For single precision and double precision FPM, we desire 47-bit and 105-bit IP shifter using 2:1 multiplexers. The IP shifter is designed and implemented using various approaches such as CMOS logic and clock-less techniques—Multi-Threshold Null Convention Logic (MTNCL) and proposed Multi-Threshold Dual-Spacer Dual-Rail Delay-Insensitive Logic (MTD3L). The IP shifter is designed in gate level by using mentor graphics EDA tools with 130 nm technology, and the proposed technique is compared with existing approaches in terms of power dissipation, delay, and power-delay product (PDP) constraints.
Published Version
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