Comparative high-k material gate spacer impact in DG-FinFET parameter variations between two structures

Abstract

<span lang="EN-GB">This paper investigates the impact of the high-K material gate spacer on short channel effects (SCEs) for the 16 nm double-gate FinFET (DG-FinFET), where depletion-layer widths of the source-drain corresponds to the channel length. Virtual fabrication process along with design modification throughout the study and its electrical characterization is implemented and significant improvement is shown towards the altered structure design whereby in terms of the ratio of drive current against the leakage current (I<sub>ON</sub>/I<sub>OFF</sub> ratio), all three materials tested being S<sub>3</sub>N<sub>4</sub>, HfO<sub>2</sub> and TiO<sub>2</sub> increases from the respective 60.90, 80.70 and 84.77 to 84.77, 91.54 and 92.69. That being said, the incremental in ratio has satisfied the incremental on the drive current as well as decreases the leakage current. Threshold voltage (V<sub>TH</sub>) for all dielectric materials have also satisfy the minimum requirement predicted by the International Technology Roadmap Semiconductor (ITRS) 2013 for which is at 0.461±12.7% V. Based on the results obtained, the high-K materials have shown a significant improvement, specifically after the modifications towards the Source/Drain. Compared to the initial design made, TiO<sub>2</sub> has improved by 12.94% after the alteration made in terms of the overall I<sub>ON</sub> and I<sub>OFF</sub> performances through the I<sub>ON</sub>/I<sub>OFF</sub> ratio value obtained, as well as meeting the required value for V<sub>TH </sub>obtained at 0.464V. The I<sub>ON</sub> from high-K materials has proved to meet the minimum requirement by ITRS 2013 for low performance Multi-Gate technology.</span>