Exploration of symmetric high-k spacer (SHS) hybrid FinFET for high performance application

Abstract

This paper evaluates the novelty aspects of symmetric high-k spacer (SHS) hybrid FinFET over conventional FinFET. The SHS hybrid FinFET combines three significant and advanced technologies i.e., 2-D ultra-thin-body (UTB), 3-D FinFET, and high-k spacer on a single silicon on insulator (SOI) platform to enhance the device performance. In these recent days, high-k dielectric spacer materials are widely explored because of their better electrostatic control and more immune towards short channel effects (SCEs) in nanoscale devices. For the first time, this paper introduces SHS hybrid FinFET and claims a useful improvement in device performances. Various parameters like subthreshold slope (SS), on–off ratio (Ion/Ioff), transconductance (gm), transconductance generation factor (TGF), gain (gm/gd), total gate capacitance (Cgg), and cut-off frequency (fT) are carefully observed with the variation of high-k spacer length (Lhk) ranging from 1 to 5 nm for the hybrid FinFET. From comprehensive 3-D device simulation, we have demonstrated that the proposed device is superior in suppressing SCEs with predicting higher drive current as compared to conventional FinFET.