Enhancement in Retention Time of 3TDRAM Using Double Gate Finfet Technology at Nanometer Regime.

Abstract

Leakage current, power and area is the key challenges for VLSI designer during implementation of low power devices. In an integrated circuit number of transistors double in small silicon area every two years. There are certain limitations of cmos technology in nanometer regime out of which leakage current, leakage power, average current and average power is an important issues. In this paper, Retention time improvement in three transistor dynamic random access memory using double gate Finfet technology is proposed. Double gate finfet technology in 3TDRAM overcomes the issues related to cmos technology and it does not required additional circuitry. Proposed 3T DRAM is investigated with cmos and finfet technology at 90nm technology using cadence tool. Analysis of 3TDRAM using cmos and double gate finfet technology is carried out by variation in supply voltage and capacitance values. In double gate finfet technology leakage parameters are minimized and retention time(Th) is more improved as compared to cmos technology is observed.