Design of Look-Up Table with Low Leakage Power Enhanced Stability 10 T SRAM Cell

Abstract

Leakage Power and cell stability are the most salient parameters that draw major attention while designing the SRAM cell. So, a new SRAM topology is proposed which reduces the Leakage power further and enhances the stability. Leakage Power is calculated and compared with existing SRAM cells and the Proposed Low Leakage Power Stable 10 T SRAM(P10T) cell. It is evaluated by making SRAM cell to operate in the idle mode of operation. There is a reduction of 29.068%, 23.23%, 39.30%, 22.58% leakage power when storing 1 in P10T SRAM cell compared with 6 T,8 T,8TG,9 T cells at TT Corner, respectively, at 0.9 V supply voltage. There is a reduction of 2.40%, 11.69%, 16.49%, 3.39% leakage power when storing 0 in P10T SRAM cell compared with 6 T, 8 T, 8 TG, 9 T at TT Corner, respectively, at 0.9 V supply voltage. Other design metrics related to the stability of the SRAM cell like HSNM, RSNM, and Write Margin are also calculated and compared. There is an increase of 19.40%, 18.71%, 19.40%, 18.71% in HSNM of P10T SRAM cell compared to 6 T, 8 T, 8 TG, and 9 T SRAM cell, respectively, at TT corner. There is an increase of 130.425%, 18.73%, 262.69%, 18.73% RSNM for the P10T SRAM cell compared to 6 T, 8 T, 8 TG, and 9 T SRAM cells, respectively, at TT corner. During Write 1, there is an increase of write margin by 29.03%, 28.61%,28.61% at TT corner at 0.9 V supply voltage. The impact of Process, Voltage and Temperature (PVT) variations on Leakage Power, HSNM, RSNM and Write Margin are evaluated. Monte Carlo Analysis with 2000 samples is performed on Leakage Power, which shows less variability for the P10T SRAM cell while storing 0. 4-input Look-Up table is implemented using 6 T and P10T SRAM cell. The LUT using P10T SRAM cell decreases the Leakage power by 8.58% than the 6 T SRAM cell. All SRAM cells are implemented in 45 nm CMOS Technology using Cadence Virtuoso.