Design of an enhanced write stability, high-performance, low power 11T SRAM cell

Abstract

ABSTRACT In the present era of diminishing technology nodes, stability and performance of SRAM cells deteriorate. To cope up with the above growing concerns, a new 11 T SRAM cell has been proposed which improves the stability in all operating modes of SRAM as well as the delay and power in the write mode. At worst process corner SS, the write 0 delay has been improved by 14.01%, 6.75%, 115.72% and 26.61% compared to 6 T, 8 TG, 10 TDiff and 11 T SRAM designs and write 1 delay has been improved by 9.2%, 88.639%, 13.69% and 71.42% compared to 6 T, 10 TDiff, DDS11T and 11 T designs at 0.9 V supply voltage. The impact of PVT variations has been studied on SNM, Write Margin, Read & Write delay, Leakage Power. The Monte Carlo simulation has been performed to study the effect of variability. P11T SRAM cell exhibits narrower spread in the distribution of majority design metrics. The removal of the half-select issue has been illustrated in the P11T SRAM cell using Monte Carlo simulations. Post-Layout simulation has been carried out to evaluate different design metrics at 45 nm technology node in Cadence Virtuoso.