Design of energy efficient N-bit vedic multiplier for low power hardware architecture

Abstract

ABSTRACT In this paper, we introduce an advanced design of an N-bit Vedic multiplier using Nikhilam Sutra and Karatsuba algorithms, tailored for low power hardware architectures. Our approach innovatively combines these ancient mathematical techniques to significantly enhance computational efficiency in digital systems. The primary novelty of our method lies in its capability to drastically reduce both power consumption and operational delay. Compared to conventional multipliers, our design demonstrates an average area reduction of 56% and a latency reduction of 45%. Additionally, the integration of the Karatsuba algorithm optimises the structural design of the multiplier, further lowering the requirements for computational units. This dual-sutra approach not only optimises energy efficiency but also enhances overall effectiveness, making it highly suitable for image and signal processing as well as biomedical applications where power efficiency is crucial. By explicitly stating these key advancements, we aim to clearly communicate the significant strides our research has made in the field of energy-efficient hardware design.