Design of High Speed Vedic Multiplier based on Nikhilam Sutra Algorithm using Successive Approximation

Abstract

The mathematical system followed in the Ancient India is Vedic Mathematics. It helps to calculate the arithmetic operations faster without any computerized system. Vedic Mathematics works on the principles of Sutra. It deals with mathematics linked with arithmetic, algebra, and geometry. These modus operandi and ideas can be directly applied to trigonometry, plain and spherical geometry, conics, differential calculus, integral calculus and applied mathematics of different kinds. There are various multipliers among them Urdhva Triyakbyam Sutra is used widely because it dissipates less power and area efficient multiplier. Nikhilam sutra is not widely used due to its limitations in the calculation of remainder. In this paper, high speed Vedic multiplier is designed by modifying Nikhilam sutra principles using bit reduction technique. In the calculation of remainder in Vedic multiplier based on Nikhilam Sutra, the addition and subtraction is done with the base value of 10 for decimal number system. For binary multiplication, base 2 is considered and 2’s complement is taken to derive the remainder in the algorithm. In this work, the remainder is calculated using bit reduction technique to reduce the complexity of the multiplier. The first two bits are reduced from the given N-bit number. Hence, the multiplier size is reduced to N-2 for remainder multiplication. Additionally, shift operations are needed to perform the multiplication of two N-bit binary numbers. By the successive application of this multiplier, higher bit length multiplier can be easily designed with less computation time. The proposed algorithm is implemented using mentor Graphics tool. The results are compared N-bit conventional multipliers and the proposed method. Comparing with conventional methods, the Wallace multiplier is the fastest multiplier. While comparing with conventional Nikhilam multiplier and Urdhva Triyakbyam multiplier, our proposed multiplier gives the result in minimum computation time. While comparing with Wallace and our proposed gives the optimum result. The proposed design is suitable for high speed compact size arithmetic applications.