Speed and Power Efficient Vedic Multiplier using Adders with MUX

Abstract

This paper project an competent vedic multiplier design using adders with multiplexer structure. To obtain faster results and optimized circuit design, Vedic multiplier is used. Multiplier determines the throughput in arithmetic operations and performance faster in many of the real time applications. Vedic Multiplier is a kind of low power and fast multipliers. Vedic multiplier by means of urdhva tiryagbhyam sutra is designed for 8-bit numbers. Here for performance analysis delay and power of a multiplier are considered. To get an effective output, we have replaced the ripple carry adder with multiplexer as an substitute instead of traditional ripple carry adder. By using this customized adder, it is possible to achieve minimum gate delay with reduced power consumption. Instead of using conventional carry save adder it is replaced with carry save adder using multiplexer in order to obtain output with high efficiency. By considering both ripple carry adder and carry save adder the speed and power parameters are compared. In Vedic Mathematics there are 16 Sutras, in which 2 Sutras namely Urdhva Tiryagbhyam Sutra and Nikhilam Sutra have been considered for the purpose of doing multiplication process for two 8-bit numbers. In this two 8-bit multiplication process, we have implemented Urdhva Triyagbhyam Sutra which is of vertical and crosswise.