Design of a High Performance 1 Kb SRAM Array Using Proposed Soft Error Hardened 12T SRAM Cell

Abstract

The shrinking of technology node and supply voltage has a profound effect on various design metrics of the SRAM cell. Available SRAM designs in the literature suffer from half-select issue, increased write delay, leakage power, read power, and lower critical charge. Considering the above concerns, a new P12T SRAM cell was proposed incorporating the cross-point selection to remove half-select issue, adding the inverter between the storage nodes to enhance critical charge, High-[Formula: see text] transistors in read path to reduce the read power and leakage power. The critical charge of P12T SRAM cell is 9.13% and 15.21% higher than the 8T and 10T SRAM cells, respectively, at 0.9[Formula: see text]V [Formula: see text]. P12T SRAM cell has 41.61% and 21.4% decrease in read power than 8T and AS10T SRAM cells, respectively, at SS corner for 0.9[Formula: see text]V [Formula: see text]. In P12T SRAM cell, write 1 PDP at worst case corner SS is [Formula: see text], [Formula: see text], [Formula: see text], [Formula: see text], and [Formula: see text] lower than 8T, AS8T, AS10T, 10T, and 12T SRAM cells, respectively, at 0.9[Formula: see text]V [Formula: see text]. Monte Carlo simulation has been done to study variability and half-select issue. 1[Formula: see text]Kb bit interleaving SRAM array is designed using P12T SRAM cell and 12T SRAM cell. 1[Formula: see text]Kb SRAM array using P12T SRAM cell has superior write PDP than 12T SRAM cell. Postlayout simulation has been carried out on all the SRAM cells to estimate different metrics in 45[Formula: see text]nm technology using the Cadence Virtuoso.