Compact Modeling of Capacitance Based 14 nm Triple Gate FinFET Using Verilog-A

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Technology down scaling process divulges, the unveiled short channel effects (SCEs), which disrupts the behavior of bulk CMOS technology. In order to overcome these unveiled effects, the single gate controlling mechanism should be replaced with multiple gate mechanism to enhance the control of gate over the conducting channel. FinFET is a promising technology, which provides efficient gate controlling over the channel by multiple gates. Some of the multi gate FinFET devices are Double gate FinFET (DG-FinFET), Triple gate FinFET (TG-FinFET). In this paper, a charge based capacitance model has been proposed for modeling of TG-FinFET. The behavior and structure of the proposed device has been described in Verilog-A scripting language. IV characteristic of the proposed device has been observed, a three stage ring oscillator circuit is implemented with the proposed device to generate 1 GHz signal for testing purpose.