Double-gate FinFET Research Articles

Effect of electron mobility variation on short channel effects in nanoscale double gate FinFETs: A comparative study

This work investigates the impact of electron mobility variations on short channel effects (SCEs) in different semiconductor materials using FinFETs. Using PADRE simulator, the work examines Gallium Arsenide (GaAs), Gallium Antimonide (GaSb), Gallium Nitride (GaN), and Silicon (Si) FinFETs, analyzing performance metrics such as Drain Induced Barrier Lowering (DIBL), Subthreshold Swing (SS) and Threshold Voltage roll-off. The result shows that GaN-FinFET exhibits lowest subthreshold swing of 63 mV/dec at electron mobility of 10000 cm2/Vs, and threshold voltage of 0.44V at electron mobility of 10000 cm2/Vs, while Si-FinFET exhibits lowest DIBL of 3 mV/V at (4000-10000) cm2/Vs. This finding contributes to advancing the understanding of short channel effects in nanoscale FinFETs and provides valuable insights for optimizing device performance in future semiconductor technologies.

Temperature-dependent short channel effects in nanoscale double gate FinFETs: A comparative study

This work investigates the impact of temperature variation on Short Channel Effects (SCEs). Gallium Arsenide (GaAs), Gallium Antimonide (GaSb), Gallium Nitride (GaN) and Silicon (Si) are the channel materials that are investigated. The study examines phenomenal metrics such as Drain Induced Barrier Lowering (DIBL), Subthreshold Swing (SS), Threshold Voltage Roll-off, On-current and Transconductance using PADRE Simulator. The results revealed that GaAs-FinFET excels in terms of DIBL, threshold voltage, transconductance and on-current at higher temperatures. On the other hand, GaN-FinFET excels in terms of SS at lower temperatures. These findings contribute to the understanding of temperature effects on nanoscale double gate FinFETs, aiding their optimization for diverse electronic devices.

Ultra low power offering 14 nm bulk double gate FinFET based SRAM cells

For many decades, SRAM cell design with low power dissipation is the problem of interest for researchers due to its numerous applications in embedded systems. In this research work, a Bulk double gate FinFET based design of SRAM cell and performance analysis is carried out. Also, a comprehensive analysis is performed on FinFET and CMOS technology based SRAM cells. The novelty in the proposed work is, the designing of the 14 nm bulk double gate FinFET transistor using the FEM tool and eventually designing the SRAM cells. The designed bulk FinFET offers an IDS of 3.5 μA/μm with HfO2 as dielectric material. By using this type of FinFET in SRAM cell design the leakage current is reduced significantly. The performance analysis on 6 T(T represents the number of transistors used in the design of SRAM cell), 7 T, 8 T and 9 T SRAM cells design with MOSFET and FinFET technologies is done in terms of leakage current, power dissipation and static noise margin. Compared with MOSFET, FinFET based SRAM cell offers low leakages especially 7 T SRAM cell has low leakage of 296.7 pW. The SRAM cells SNM value is also improved by 10 %.

Statistical Optimization Influence on High Permittivity Gate Spacer in 16nm DG-FinFET Device

In this paper, the effect of high permittivity gate spacer on short channel effects (SCEs) for the 16 nm double-gate finFET is investigated, with the output responses optimized using L9 orthogonal array (OA) Taguchi method. The determination is done through Signal-to-noise ratio to the effectiveness of the process parameters towards four output responses such as threshold voltage (VTH), drive current (ION), leakage current (IOFF) and Subthreshold Swing (SS). The virtual fabrication of the 16 nm double-gate fin FET was performed using ANTHENA module while the electrical characteristics of the device were simulated using ATLAS module. These two modules were combined with Taguchi method to aid in designing and optimizing the process parameters. The electrical characterization was performed and significant improvement could be seen on the TiO2 and HfO2 material in terms of the ION/IOFF ratio obtained at 4.03106 and 3.61106 respectively for 0.179±12.7% V of VTH. It can be observed that when approaching a higher value of dielectric constant (high-K), the ION increases while the SS and IOFF decreases. As conclusion, the output responses from high-K materials have been proven to meet the minimum requirement by International Technology Roadmap Semiconductor (ITRS) 2013 for high performance Multi-Gate technology for the year 2015.

Enhancement in Retention Time of 3TDRAM Using Double Gate Finfet Technology at Nanometer Regime.

Leakage current, power and area is the key challenges for VLSI designer during implementation of low power devices. In an integrated circuit number of transistors double in small silicon area every two years. There are certain limitations of cmos technology in nanometer regime out of which leakage current, leakage power, average current and average power is an important issues. In this paper, Retention time improvement in three transistor dynamic random access memory using double gate Finfet technology is proposed. Double gate finfet technology in 3TDRAM overcomes the issues related to cmos technology and it does not required additional circuitry. Proposed 3T DRAM is investigated with cmos and finfet technology at 90nm technology using cadence tool. Analysis of 3TDRAM using cmos and double gate finfet technology is carried out by variation in supply voltage and capacitance values. In double gate finfet technology leakage parameters are minimized and retention time(Th) is more improved as compared to cmos technology is observed.

Comparative Analysis of FINFETS and MOSFETS

This paper makes a brief introduction of CMOS technology and illustrates the structure of traditional MOSFETs and Fin-FETs and their developing process. To help better understand advantages and drawbacks of both two technologies, it also explains the Drain Induced Barrier Lowering (DIBL) effect and its impact on transistor performance. The paper compares the DIBL ratio of Double-Gate Fin-FETs and Double-Gate MOSFETs by varying channel length using Fin-FET and MOSFET in similar structural parameters. The results are shown in different diagrams, which proves that Fin-FETs have a better control of DIBL effect than conventional MOSFETs. In the end it explains the shortcomings of the experiment and describes future expectations for Fin-FET technology.

Design of 0.8V, 22 nm DG-FinFET based efficient VLSI multiplexers

Conventional CMOS has become successful logic for most digital VLSI circuits and a good candidate in terms of power dissipation. But due to its dual nature, more transistors are required and are not suitable as the technology is scaled down. This paper proposes a Double Gate (DG) FinFET based 4-1, 8-1, 16-1 multiplexer (DFMs) with a reduced number of transistors catering to the needs of low-power dissipation and high speed. For designing the proposed 4-1 DG-FinFET digital multiplexer (DFM) circuit requires only 16 FinFETs. Compared to the CMOS multiplexer circuit's conventional architecture, the proposed 4-1 DFM design uses a single pull-up FinFET in its first stage, and the second stage has only 4 FinFETs. The DFM circuit design is extended to 8-1 and 16-1 targeting to reduce transistor count, delay, and power dissipation. Extensive simulations are done at a 22 nm technology node using Eldo software of Mentor Graphics. With the simulated results of proposed and conventional CMOS designs at different supply voltages and load capacitances on the 22 nm technology node, the proposed DFM multiplexers' power-delay product is better. For 1 GHz of frequency and the least feasible supply voltage of 0.8 V, the proposed digital multiplexer attains a 10% reduction in power dissipation and a 6% reduction in delay. Including inverters in the designs, the transistor count is also less compared to the conventional static multiplexer.

DGFinSAL: A New Low Power Adiabatic FinFET-Based Logic Family for DPA-Resistant Applications

In this paper, a novel low power, adiabatic, DPA-resistant logic family based on double-gate FinFET transistors is presented. Internet-of-Things devices have gained many applications in all aspects of human life. Therefore, the security and energy efficiency of such device is very important. Radio-frequency identification tags and wireless sensor networks use AES modules to encrypt secret information. Attackers have successfully tampered these modules using differential power analysis (DPA) attacks. Therefore, DPA-resistant circuits with high immunity are desirable. The proposed logic circuit family has been simulated using HSPICE and PTM 20 nm technology parameters. Simulation results show that the proposed logic circuits consume lower power up to 40% in comparison with the previous designs. Furthermore, the security of the proposed logic is evaluated using an 8-bit SBOX as a test bench circuit. It has been shown that the proposed design is immune to a DPA, through simulated attacks using Cadence Virtuoso and MATLAB software.

Comparative performance of the ultra-short channel technology for the DG-FinFET characteristics using different high-k dielectric materials

The downscaling of the SOI-MOSFET device has an important role of the advanced technology in the semiconductor industry, so the researchers aim to find the structure which can improve the considerable reduction, this paper is investigated a proposal novel device in the nanoscale technology of the double-gate FinFET using different high-k materials gate (SiO2, SnO2, ZrO2 and Ta2O5) for the ultra-short gate Lg = 5 nm on different parameters such as: the subthreshold voltage (SS), the threshold voltage (Vth), the transconductance (gm), the ON and OFF currents (Ion, Ioff) and also the Ion/Ioff ratio and the electrical field (E) by the three-dimensional TCAD-SILVACO simulator. The results reveal that the Ta2O5 material of gate with high permittivity (k = 27) turns out better values for (Vth, SS, ON, OFF current and ON/OFF ratio current, gm, electrical field (E)) in comparison with other dielectric SiO2, SnO2, ZrO2 which improve the performance of the device

Modeling, Simulation and Analysis of Surface Potential and Threshold Voltage: Application to High-K Material HfO2 Based FinFET

In this study, an analytical model for surface potential and threshold voltage for undoped (or lightly) doped tri-gate Fin Field Effect Transistor (TG-FinFET) is proposed and validated using transistor computer aided design (TCAD) simulation. The threshold voltage with channel length 50 nm was compared with the published experimental results achieved from tri-gate FinFET. Separate solutions of 2D Poisson’s equation were obtained for both symmetric and asymmetric double gate FinFET and combined using the perimeter-weighted sum approach to achieve the surface potential for TG-FinFET. The inversion charge model was used to find the threshold voltage of the above mentioned device. The results of the model were obtained for different channel lengths, fin widths and fin heights on the silicon substrate. A comparative study of hafnium dioxide (HfO2) and silicon dioxide (SiO2) for the same oxide thickness was delineated to depict the influence of the high dielectric material on the model of FinFET. As anticipated, the oxide thickness of HfO2 is greater than SiO2 to maintain the same surface potential. The result of the analytical model was well agreed with the TCAD simulation outcome. Hence, it can be considered as a promising model in device technology.

Compact Modeling of Capacitance Based 14 nm Triple Gate FinFET Using Verilog-A

Technology down scaling process divulges, the unveiled short channel effects (SCEs), which disrupts the behavior of bulk CMOS technology. In order to overcome these unveiled effects, the single gate controlling mechanism should be replaced with multiple gate mechanism to enhance the control of gate over the conducting channel. FinFET is a promising technology, which provides efficient gate controlling over the channel by multiple gates. Some of the multi gate FinFET devices are Double gate FinFET (DG-FinFET), Triple gate FinFET (TG-FinFET). In this paper, a charge based capacitance model has been proposed for modeling of TG-FinFET. The behavior and structure of the proposed device has been described in Verilog-A scripting language. IV characteristic of the proposed device has been observed, a three stage ring oscillator circuit is implemented with the proposed device to generate 1 GHz signal for testing purpose.

Device-Circuit Interaction and Performance Benchmarking of Tunnel Transistor-Based Ex-OR Gates for Energy Efficient Computing

This paper explores the design and analysis of 20[Formula: see text]nm tunnel transistor-based Exclusive-OR (Ex-OR) gates and half-adder cells with circuit interaction (co-design) approach for energy efficient and reliable computing architectures at scaled supply voltages (50–300[Formula: see text]mV). TFETs have attracted much attention recently for energy efficient system designs. The circuit interaction is made possible for designing more consistent functional architectures at the minimum power supply of 50–300[Formula: see text]mV. Using this technique, the core computational blocks of basic adder blocks and Ex-OR gates are designed with TFET as a fundamental device and the whole design procedure is elaborated in this paper. The primary classifications of Tunnel FETs, viz. Homo-junction TFET (HoJn TFET) and Hetero-junction TFETs (HeJn TFET) are investigated thoroughly under different constraints specifically at the device configurations. By considering the above-mentioned subtypes of TFETs, three variants of Ex-OR primitive gates are modeled and are named with respect to the use of transistors as static complementary TFET-12T (SC12T), Transmission Gate logic-8T (TG8T) and Improved Transmission Gate logic-6T (ITG6T) Ex-OR gate designs. The benchmarking of the proposed gates is done using double-gate Si FinFET at 20[Formula: see text]nm technology. Amongst all the three proposed Ex-OR designs of SC12T, TG8T and ITG6T in addition to that of LVT and HVT FinFET/CMOS, only ITG6T is the designer’s choice by offering the minimum power consumption as well as high energy, improved choice compared to the other two styles of designs and also when robustness and reliability are taken into account, SC12T and TG8T designs are not providing the full swing of outputs. The minute glitch with that of ITG6T designs is a lesser reliability feature and for this the best alternative is TFET TG8T by providing suppressed over shoots and enhanced transition speed. From the performed multi simulations under different critical conditions and at supply voltage of 100[Formula: see text]mV, it is being demonstrated that the energy efficient circuit option is the SC12T and ITG6T Ex-OR designs which are validated with the steep slope characteristics of TFET’s and also these two designs offer reliability advantage. The major restrictions from the energy efficiency issues are eliminated and disclosed in the HoJn TFETs and HeJn TFET by using circuit co-design methodology and TFETs steep slope characteristics.

Optimization of 16 nm DG-FinFET using L25 orthogonal array of taguchi statistical method

<span>The impact of the optimization using Taguchi statistical method towards the electrical properties of a 16 nm double-gate FinFET (DG-FinFET) is investigated and analyzed. The inclusion of drive current (I<sub>ON</sub>), leakage current (I<sub>OFF</sub>), and threshold voltage (V<sub>TH</sub>) as part of electrical properties presented in this paper will be determined by the amendment of six process parameters that comprises the polysilicon doping dose, polysilicon doping tilt, Source/Drain doping dose, Source/Drain doping tilt, V<sub>TH</sub> doping dose, V<sub>TH</sub> doping tilt, alongside the consideration of noise factor in gate oxidation temperature and polysilicon oxidation temperature. Silvaco TCAD software is utilized in this experiment with the employment of both ATHENA and ATLAS module to perform the respective device simulation and the electrical characterization of the device. The output responses obtained from the design is then succeeded by the implementation of Taguchi statistical method to facilitate the process parameter optimization as well as its design. The effectiveness of the process parameter is opted through the factor effect percentage on Signal-to-noise ratio with considerations towards I<sub>ON</sub> and I<sub>OFF</sub>. The most dominant factor procured is the polysilicon doping tilt. The I<sub>ON</sub> and I<sub>OFF</sub> obtained after the optimization are 1726.88 μA/μm and 503.41 pA/μm for which has met the predictions of International Technology Roadmap for Semiconductors (ITRS) 2013. </span>

Optimization of process parameter variations for 16nm DG-FinFET using Response Surface Methodology-Central Composite Design

A 16 nm double-gate FinFET (DG-FinFET) designed are optimized with a mathematical modelling using a response surface method-central composite design (RSM-CCD), with the relationship between parameters and output responses are investigated and examined. The threshold voltage (VTH), drive current (ION), leakage current (IOFF) and subthreshold swing (SS) ramifications towards the adjustment of six process parameter that integrates polysilicon doping dose, polysilicon doping tilt, Source/Drain doping dose, Source/Drain doping tilt, VTH doping dose and VTH doping tilt is studied using the RSM-CCD using half-factorial of 86 experimental runs, which totals to 52 runs, consisting of 8 centre points, 12 axial points, and 32 factorials. Ultimately, the VTH after the result is optimized with RSM-CCD showcased an improvement at 0.1785 V, with IOFF achieved at 958.71 pA/μm despite performing less favourably after optimized. That said, an improvement towards ION/IOFF ratio at 2.049×106 compared to 1.666×106 proves that both optimization techniques have met the predictions of International Technology Roadmap for Semiconductors (ITRS) 2013.

Study of Carrier Scattering and Quantization Effects in Steep Retrograded Double Gate FinFETs for Nano Technology Applications

In this paper, a study has been carried out on aDouble Gate FinFET (DG-FinFET) to evaluate its performance. The effect of electric field on the confinement of carries in the centre of the channel and also effect on the velocity of electrons i.e. velocity saturation concept has been depicted clearly. The study shows that the critical parameters like Subthreshold and DIBL can be greatly improved and are found to be stable with applied drain bias with the application of an additional gate in the traditional device.

Investigation of Inversion Charge Characteristics and Inversion Charge Loss for InGaAs Negative-Capacitance Double-Gate FinFETs Considering Quantum Capacitance

This paper investigates the inversion charge characteristics and quantum-capacitance induced inversion charge loss for In 0.53 Ga 0.47 As negative-capacitance FinFETs (NC-FinFETs) using theoretical calculation corroborated with numerical simulation. Our study indicates that, the boost of inversion charges due to negative capacitance increases with increasing remnant polarization Pr. In addition, the inversion charge boosting for the In 0.53 Ga 0.47 As device is significantly larger than that of the Si (110) device due to the step-like inversion capacitance characteristic stemming from the 2D density-of-states of the In 0.53 Ga 0.47 As device. In other words, the quantum-capacitance induced inversion-charge loss for III-V channel can be mitigated in NCFETs.

Leveraging Independent Double-Gate FinFET Devices for Machine Learning Classification

Mixed-signal machine learning (ML) classification has recently been demonstrated as an efficient alternative for classification with power expensive digital MOSFET circuits. In this paper, a topology based on independent double-gate (IDG) FinFET devices is proposed for classifying high-dimensional input data into multi-class output space with less power and area as compared with state-of-the-art MOSFET classifiers. To facilitate a high-resolution multiplication as a part of the classifier predictions, ML features and feature weights are, respectively, fed to the back and front gate inputs of the individual IDG-FinFET transistors. A classifier that considers the decisions of the individual predictors is designed at 30 nm FinFET technology node and operates at 333 MHZ with nominal supply voltage of one volt. To evaluate the performance of the classifier, a reduced MNIST dataset is generated. The original resolution is reduced from $28 \times 28$ features to $9 \times 9$ features and the most important features are selected with sequential backward selection algorithm. The system is simulated in SPICE, exhibiting prediction accuracy of 90%, energy consumption of 25 pJ per classification (over four times lower than similar state-of-the-art classifiers), area of 1,365 ${\mu }\text {m}^{2}$ , and a stable response under a wide range of system variations.

Comparative high-k material gate spacer impact in DG-FinFET parameter variations between two structures

<span lang="EN-GB">This paper investigates the impact of the high-K material gate spacer on short channel effects (SCEs) for the 16 nm double-gate FinFET (DG-FinFET), where depletion-layer widths of the source-drain corresponds to the channel length. Virtual fabrication process along with design modification throughout the study and its electrical characterization is implemented and significant improvement is shown towards the altered structure design whereby in terms of the ratio of drive current against the leakage current (I<sub>ON</sub>/I<sub>OFF</sub> ratio), all three materials tested being S<sub>3</sub>N<sub>4</sub>, HfO<sub>2</sub> and TiO<sub>2</sub> increases from the respective 60.90, 80.70 and 84.77 to 84.77, 91.54 and 92.69. That being said, the incremental in ratio has satisfied the incremental on the drive current as well as decreases the leakage current. Threshold voltage (V<sub>TH</sub>) for all dielectric materials have also satisfy the minimum requirement predicted by the International Technology Roadmap Semiconductor (ITRS) 2013 for which is at 0.461±12.7% V. Based on the results obtained, the high-K materials have shown a significant improvement, specifically after the modifications towards the Source/Drain. Compared to the initial design made, TiO<sub>2</sub> has improved by 12.94% after the alteration made in terms of the overall I<sub>ON</sub> and I<sub>OFF</sub> performances through the I<sub>ON</sub>/I<sub>OFF</sub> ratio value obtained, as well as meeting the required value for V<sub>TH </sub>obtained at 0.464V. The I<sub>ON</sub> from high-K materials has proved to meet the minimum requirement by ITRS 2013 for low performance Multi-Gate technology.</span>

Threshold voltage modeling for a Gaussian-doped junctionless FinFET

This work presents two-dimensional (2D) analytical modeling of the threshold voltage of a double-gate junctionless FinFET with a Gaussian-doped channel by evaluating the 2D electrostatic potential distribution across the active area of the device. The influence of the fringing field lines through the spacer is also included in the modeling. To confirm the validity of the derived analytical model, technology computer-aided design (TCAD) device simulations were carried out. Furthermore, the impact of various design parameters on the threshold voltage was also studied.

3D Double Gate FinFET Construction of 30 nm Technology Node Impact Towards Short Channel Effect

<p>This paper presents an investigation on properties of Double Gate FinFET (DGFinFET) and impact of physical properties of FinFET towards short channel effects (SCEs) for 30 nm device, where depletion-layer widths of the source-drain corresponds to the channel length aside from constant fin height (HFIN) and the fin thickness (TFIN). Virtual fabrication process of 3-dimensional (3D) design is applied throughout the study and its electrical characterization is employed and substantial is shown towards the FinFET design whereby in terms of the ratio of drive current against the leakage current (ION/IOFF ratio) at 563138.35 compared to prediction made by the International Technology Roadmap Semiconductor (ITRS) 2013. Conclusively, the incremental in ratio has fulfilled the desired in incremental on the drive current as well as reductions of the leakage current. Threshold voltage (VTH) meanwhile has also achieved the nominal requirement predicted by the International Technology Roadmap Semiconductor (ITRS) 2013 for which is at 0.676±12.7% V. The ION , IOFF and VTH obtained from the device has proved to meet the minimum requirement by ITRS 2013 for low performance Multi-Gate technology.</p>