SRAM Cell Design Research Articles

Design of a Radiation-Hardened SRAM Cell using 16nm Technology Node

Electronic circuits are exposed to very high energy radiation in the harsh conditions of outer space. This leads to soft errors such as single-event upsets (SEU), double-event upsets (DEU) and single-event transients (SET). The memory circuits are the most susceptible to these soft errors resulting in severe data loss. This paper proposes the design for an SRAM cell that is radiation hardened by design (RHBD). A comparative study of the standard SRAM cell and the RHBD SRAM cell indicates that the proposed design is resilient to SEUs and DEUs. The proposed design is an improvement on the 8T SRAM cell design and includes a 20T triple interlocked cell (TICE) design. The error correction capabilities of both designs are compared by manually injecting bit upsets at crucial nodes in the circuit. It is observed that the TICE design provides a 96.75% and 98.5% improvement over the standard 8T cell for 1-0 and 0-1 bit upsets respectively. The proposed design has been implemented using the 16nm model from the Arizona State University’s Predictive Technology Model (ASU-PTM), and the LTSpice software was used to carry out the simulations. Tools used: LTSpice v17 is the tool used to design the schematic circuits and to obtain the simulation results. The library file used to design the schematic is the 16nm technology node from the library of the Arizona State University’s Predictive Technology Model (ASU-PTM). Methods: To perform a comparative study of the 8T SRAM and 20T TICE, the schematic circuits were designed using the 16nm technology node in LTSpice. A baseline for the expected voltages of logic 0 and logic 1 is established before injecting errors at the sensitive voltage nodes of the circuit. The next step is to manually inject bit upsets at the crucial nodes of the memory cell to induce either a 0-1 upset or a 1-0 upset. The read/write operation is carried out along with the error injection to compare the error mitigation capacity of the circuits. Finally, the results are tabulated to prove that the 20T TICE is resilient to soft errors arising from exposure to high radiation. Results: During the normal operation of the 8T SRAM cell, the observed output voltage corresponding to logic 0 and logic 1 are 25mV and 780mV respectively. The voltage levels increased to 400mV during a 0-1 upset and dropped to 25mV during a 0-1 bit upset. This indicates that the cell is not reliable. In case of the 20T RHBD cell, the voltage levels for the normal operation were 5mV (logic 0) and 780mV (logic 1). The major improvement is shown in the case where the 20T TICE is injected with bit upsets, since it delivers a voltage of just 6mV during a 0-1 bit upset and maintains a voltage of 770mV during a 1-0 bit upset. Conclusion: The work performs the schematic designs for the comparison of the error mitigation capabilities of a 8T SRAM cell and a 20T TICE which is radiation hardened by design. The study proves that the 20T cell is capable of successfully mitigating both a 1-0 bit upset and a 0-1 bit upset

Simulation based analysis of HK-Ge-Step-FinFET and its usage as inverter & SRAM

This paper deals with comparative simulation of High-k dielectrics -Germanium Step FinFET (HK-Ge-Step-FinFET) device with reference Step FinFET. For the first time we have investigated the impact of various dimensional parameters like oxide thickness tox, gate length Lg, drain bias voltage Vds on the performance of Proposed and Reference FinFET devices. These FinFET structures have been designed and simulated in Sentaurus TCAD and Cadence Virtuoso. The electrical parameters such as current ratio ION/IOFF, Sub-threshold Swing SS , Drain Induced Barrier Lowering (DIBL), threshold voltage Vth, gate capacitance, intrinsic delay and transconductance are extracted at 10 nm gate length. It is noticed that there is a significant improvement of 28 times and 23 times in ION for proposed device over reference FINFET at Vds = 1 V and Vds = 0.5 V respectively, improvement in ION/IOFF ratio from 8.05 × 108 to 6.65 × 1010, SS of 63.21 mV/decade to 61.5 mV/decade and excellent threshold voltage of 0.18 V in proposed FinFET. The characteristics of the proposed SRAM cell including, static noise margin (SNM), read/write delay, and subthreshold leakage power, are compared with the conventional 6 T SRAM cells. It is reported that the FinFET SRAM cell has RSNM, HSNM, and WNM of 285 mV, 360 mV, and 302 mV, respectively, at Vds = 1 V. Furthermore, the suggested device-based SRAM cell outperforms traditional SRAM cells at 1.0 V in terms of read noise margin, hold noise margin, and write noise margin, as well as leakage power. Thus, it may prove to be a viable option for lowering leakage components, making it effective for low-power and high-performance inverter and SRAM cell design in the nanoscale regime.

Leakage Power Attack-Resilient Design: PMOS-Reading 9T SRAM Cell

Non-invasive side-channel attacks (SCAs) based on leakage power analysis (LPA) have received more attention recently, since leakage current has gradually become more dominant with further scaled technologies. For SRAM cells, LPA exploits the correlation between data in memory cells and their corresponding leakage power. This paper proposes a novel SRAM design in 7 nm node for countering LPA attacks, based on a single-ended PMOS-reading 9T (nine-transistor) cell design. The leakage current imbalance, delay, stability, and robustness of SRAM cells are examined for the proposed memory cell architecture with layout designs, and results are compared against other SRAM cell designs. Simulation results and failure of LPA attacks in case studies confirm the enhanced resilient behavior for the new SRAM cell design.

Design and Implementation of High Speed SRAM Cell

Static Random Access Memory's main design goals are to have a consuming low power and high speed, as technology is developing at a faster paceand this has given rise to new challenges.The high speed along with stability of SRAM are important issues to improve efficiency and performance of the system. This proposed work presents design and implementation of 1Kb 6T SRAM using CMOS technologies by using EDA tool. In this proposed work, SRAM’s cell is operated in 1V voltage. Our proposed high speed SRAM consisting 6T achieved read delay and write delay of 29.4ps & 15ps respectively. And also our designed cell has stability of 70 mV & 195 mV for read SNM and write SNM respectively

Design of improved write and read performance 12T sram cell with leakage power control technique

Currently, memory occupies nearly eighty-five percent of the allocated chip area. Integrated electronics, such as workstations and mobile gadgets, need quick memory systems that use low power. Scaling issues make it impossible to obtain low-power and resilient SRAM cells, which are critical for Internet of Things (IoT) devices, using CMOS semiconductor technology. New nanoscale technologies, like FinFET, are being proposed as a substitute for CMOS in SRAM architecture. The study introduces a novel 12T SRAM cell design using FinFET technology, including differential writing and single-ended reading operation facilitated by write-read circuitry. The cell employs a write-assist-based approach to enhance the stability of reading and writing operations accordingly. In addition to differential writing architectures, single-ended reading decreases power use, while stacking transistors and minimizing read bit-line leakage minimizes leakage power utilization. The cell's performance has been evaluated utilizing a Cadence Spectre simulator featuring 18-nm FinFET technology and compared to current SRAM architectures at a supply voltage of 0.8 V. PVT variations are conducted to evaluate the efficiency of the suggested SRAM design. The reading and writing stability of the new SRAM cells has been enhanced by a minimum of 10 % when compared with the current counterparts. A 15 % decrease in power consumption has been seen in the suggested design compared to conventional SRAM cells of the same technology.

Negative capacitance FET based dual-split control 6T-SRAM cell design for energy efficient and robust computing-in memory architectures

A Negative Capacitance Field effet transistor (NCFET) based Dual split control (DSC) 6T-SRAM cell has been designed and explored with Computing-in memory (CiM) architecture for energy efficient demonstration of Deep neural networks (DNN) basic operation such as Input-Weight (Dot) Product. The impact of ferro electric layer thickness (Tfe) on the SRAM cell perfomance metrics such as read noise margin (RNM), write noise margin (WNM) and energy efficiency for read and write operations have been analyzed at supply voltages of 0.3 V and 0.5 V. It has been observed that due to the steep slope characteristics, the NCFET based DSC 6T-SRAM cell design exhibits better RM, WM, and energy efficiency as compared to the baseline CMOS DSC SRAM cell design at VDD = 0.3 V and 0.5 V respectively (with Tfe range of 1 nm to 3 nm). Further, NCFET dual split control scheme for 6T-SRAM cell demonstrate improved read stability and write ability when compared with NCFET 6 T-SRAM cell design along with improved energy efficiency. NCFET based DSC 6T-SRAM CiM cell design has ∼22.77× and 12.41× lower energy consumption compared to the équivalent baseline 40 nm CMOS/baseline SRAM CiM design and ∼ 25.80× and 22.76× lower energy consumption compared to the NCFET based SRAM CiM at VDD = 0.3 V and 0.5 V respectively. NCFETs have improved steep subthreshold slope characteristics at an optimal Tfe value and NCFET SRAM based CiM circuits are expected to have higher noise margins and lower energy consumption compared to the baseline CMOS designs and are effective for NCFET based computing in-memory architectures with reduced read disturb issues in combination with DSC concept.

Comparison between Power Dissipation and Propagation Delay on 6T SRAM Cell Design Using GDI Logic with Transmission Gate VMSA and Voltage Divider

The rapid evolution of the semiconductor industry has witnessed shrinking portable and mobile devices alongside an increasing demand for extended battery life. Addressing the critical challenges of speed and battery life in digital devices, this paper investigated the effectiveness of innovative low-power design techniques. Focusing on the Gate Diffusion Input (GDI) approach, a recent advancement in the field, a comprehensive analysis revealed its significant potential for reducing power consumption in digital circuits. Additionally, a comparative analysis was conducted to evaluate the performance of conventional 6T GDI SRAM cells and their Modified 6T GDI SRAM with Voltage Divider, considering the influence of Sense Amplifiers. Simulation data demonstrated that Modified 6T SRAM designs, particularly the Voltage Divider and TGVMSA variants, achieved significantly lower power dissipation and delay despite having a larger cell area. Remarkably, the proposed design substantially improved power dissipation and propagation delay, achieving 1.3 ps, and 889.41mV at 1.8V shows that the suggested design enhances power dissipation and propagation delay. These findings suggest that the proposed design offers a promising strategy for enhancing power efficiency and performance in digital devices, thereby mitigating the limitations of battery life and speed in the modern technological landscape.

Design of low power low area SRAM cell at 180 nm, 90 nm and 45 nm technology nodes

Design of low power low area SRAM cell at 180 nm, 90 nm and 45 nm technology nodes

Design of low power SRAM cells with increased read and write performance using Read - Write assist technique

The demand for enhancing the performance of reliable processors necessitates using dependable, energy-efficient, and high-speed memory. Multiple obstacles arise as a consequence of this enhancement at lower technological nodes. Process, voltage, and temperature fluctuation significantly influence several performance characteristics, making it a crucial concern in nanometer SRAM design. This study presents two novel SRAM designs that effectively decrease power consumption during read operations without compromising performance or stability. A 14T SRAM has been built with an architecture that enables single-ended write and differential read operations. In addition, a 13T SRAM has been developed using an architecture that incorporates a differential write and single-ended read operation with the assistance of a write-read circuit. The two suggested SRAM cells have been fabricated using the CMOS 45 nm technology. The provided study examines the impact of modifications in process parameters on several design metrics, including the proposed cell's read-write power and current. These metrics are then compared with those of a previously suggested SRAM cell. The read power consumption of the 14T SRAM cell is reduced by 20 %, 60.63 %, 34.73 % 53.68 %, when compared to CS6T, SS8T, SS10T, and SEW10T. For the proposed 13T SRAM, the read power consumption is reduced by 147.40 %, 230.43 %, 178.2 % 217.39 %, 30.4 % when compared to CS6T, SS8T,SS10T, SEW10T, SER11T. Also the proposed SRAM II has 106.52 % lower read power when compared with proposed 14T SRAM. Also the write power of the proposed 13T SRAM is at lower side when compared to others but at the sametime write power of proposed 14T suffers from higher power consumption. Therefore the proposed 13T SRAM has been considered for the further evaluation. The RSNM and WSNM show atleast 5 % improvement when compared to existing architectures.

High performance radiation-hardened SRAM cell design for robust applications

This work proposes a high-performance 16-transistor radiation-hardened SRAM cell (HP16T), which recovers from all single event upsets and from the internal node pair multiple-node upset. The proposed HP16T cell uses a separate read path through its internal nodes and demonstrates high read stability. The HP16T cell has 6.36 times higher read stability than recently proposed RHD14T cell. The write stability of the HP16T is also high, and is 1.71 times higher than that of the recently proposed HP12T cell. The HP16T cell has the shortest write access time among existing SRAM cells, and is 1.72 times smaller than that of the RSP14T cell. Compared to the existing designs, HP16T can withstand a larger amount of the critical charge, contains fewer susceptible nodes, and has the least single event upset occurrence probability. The figure of merit (FOM) is used to assess the overall performance, and the proposed HP16T exhibits the best FOM among the referenced SRAM cells.

Design of two-port SRAM cell with improved write operation

In this paper, a novel seven-transistor (7T) two-port SRAM cell incorporating an assist circuit is proposed. Wherein, the assist circuit is used to deal with the memory cell failures. During a write operation, this circuit is activated to connect a diode-connected transistor to the source of the drive transistor located near the write bit line. Accordingly, it can provide an efficient solution to the writing ‘1’ issue to improve write operations in this manner. Simulation results for the proposed cell design confirm that there is a conspicuous improvement over the conventional two-port SRAM cells and fast writing also can be achieved.

Soft-Error-Aware Radiation-Hardened Ge-DLTFET-Based SRAM Cell Design

In this paper, a soft-error-aware radiation-hardened 6T SRAM cell has been implemented using germanium-based dopingless tunnel FET (Ge DLTFET). In a circuit level simulation, the device-circuit co-design approach is used. Semiconductor devices are very prone to the radiation environment; hence, finding out the solution to the problem became a necessity for the designers. Single event upset (SEU), also known as soft error, is one of the most frequent issues to tackle in semiconductor devices. To mitigate the effect of soft error due to single-event upset, the radiation-hardening-by-design (RHBD) technique has been employed for Ge DLTFET-based SRAM cells. This technique uses RC feedback paths between the two cross-coupled inverters of an SRAM cell. The soft-error sensitivity is estimated for a conventional and RHBD-based SRAM cell design. It is found that the RHBD-based SRAM cell design is more efficient to mitigate the soft-error effect in comparison to the conventional design. The delay and stability parameters, obtained from the N-curve, of the Ge DLTFET-based SRAM cell performs better than the conventional Si TFET-based SRAM cell. There is an improvement of 305x & 850x in the static power noise margin and write trip power values of the Ge DLTFET SRAM cell with respect to the conventional Si TFET SRAM cell.

Design of a high performance CNFET 10T SRAM cell at 5nm technology node

This article proposes a CNFET 10T SRAM cell based on Stanford Virtual Source model at 5nm technology node, through optimization design and simulation analysis to select optimum gate widths of transistors to ensure best performance in terms of stability, speed and power consumption. We compare the proposed 10T CNFET SRAM with the optimized 6T CNFET SRAM in [9]. It was found that the timing and power characteristics of the proposed 10T SRAM cell is better than that of the 6T structure, the static power consumption is greatly reduced while the RSNM is improved by 93.5%, read and write EDP are improved by 68.5% and 96%, respectively.

A negative capacitance FET based energy efficient 6T SRAM computing-in-memory (CiM) cell design for deep neural networks

An Energy-Efficient Computing-in-Memory (CiM) cell design utilizing a Negative Capacitance (NC) FET has been proposed to support computing architectures for Deep Neural Networks (DNNs). The NCFET device characteristics for CiM architectures have been studied to determine an optimal device performance window by changing the thickness of ferroelectric layer (Tfe). The performance metrics such as read margin (RM), write margin (WM), read energy and write energy of NCFET 6 T SRAM cell are analyzed with varying Tfe at two different supply voltages 0.3 V and 0.5 V respectively. NCFET based SRAM cell design achieves higher RM and WM at Tfe of 3 nm and lower energy consumption at 1 nm Tfe as compared with the baseline SRAM cell design at both VDD = 0.3 V and VDD = 0.5 V respectively. 6 T NCFET based CiM cell design for performing basic input-weight product operation (IWP) has been demonstrated and performance comparison is done with baseline CMOS design at VDD = 0.3 V and VDD = 0.5 V. In comparison with the baseline CMOS CiM cell design, NCFET based SRAM CiM design achieves ∼2.59x and 1.62x lower energy consumption at VDD = 0.3 V and VDD = 0.5 V respectively with an optimal Tfe window of 1–3 nm.

Design and Analysis of a Radiation Resistant 12T SRAM Cell for Aerospace Applications

Introduction: Advanced low-power designs have been scaled down to the device parameters that increase single-event multi-node upset in memory elements. This degradation of the stability of the memory elements in aerospace applications is due to the high radiation environment and rapid temperature changes. Method: Hence, this paper presents a comprehensive treatment model for hardened storage elements with a soft error resulting in multi-node upset. A novel 12T SRAM memory cell configuration has been proposed, analysed, and simulated using Cadence Virtuoso gpdk 45 nm CMOS technology. Result: The proposed design counteracts the positive feedback induced due to the charged ion strike, as in past technical literature. The radiation environment has been realized with double exponential current sources, and temperature analysis has been carried out under parametric analysis. Conclusion: The novel 12T achieves good stability and remains resilient to bit-flip due to ion strikes for a wider range of voltage when the temperature varies from -50oC to 200oC. Moreover, the proposed structure features a lower susceptibility to single event upset, less write and read time, and reduced area compared to the reported RSP 14T.

Transmission Gate Based 8T SRAM Cell for Biomedical Applications

Abstract: There is an immense necessity for several kB of embedded memory for Biomedical systems which typically operate in the sub-threshold domain with perfect efficiency. SRAMS dominates the total power consumption and the overall silicon area, as 70% of the die has been occupied by them. This brief proposes the design of a Transmission gate-based SRAM cell for Biomedical applications eliminating the use of peripheral circuitry during the read operation. This topology offers a smaller area, reduced delay, low power consumption, and improved data stability in the read operation. Static Random Access Memories mostly contribute to the performance, area, and power dissipation of digitally integrated systems. The mentioned implantable and wireless applications require low-power circuits operating for a long time, occupying less area without degrading the performance, as it provides inconvenience and may even be risky especially while considering the implantable devices.

Design of soft-error resilient SRAM cell with high read and write stability for robust operations

This paper proposes a highly robust 16 transistor soft-error resilient SRAM cell (SERSC-16T) to provide complete resilience to single event upsets (SEU). The proposed cell is complete resilient to SEU at any sensitive node and also shows recovery from the double-node-upset to its fixed internal node pair. Owing to its separate read path through an internal node, the proposed cell offers the highest read-stability, 6.8 times higher than the state-of-the-art cell RHD-14T. The proposed cell also shows the fastest write operation and its write access time is 1.6 times less compared to the recently proposed cell SCCS-18T. In addition, the proposed cell has 1.7-times higher write stability compared to state-of-the-art cell HP-12T. The SERSC-16T cell also shows moderate leakage power dissipation, which is 1.5 times less compared to the SCCS-18T cell. Moreover, the proposed cell shows the best figure of merit and the most negligible probability of SEU occurrence among all state of the art radiation hardened SRAM cells.

A 7T high stable and low power SRAM cell design using QG-SNS FinFET

System on Chip (SoC) low power cache memories are in great demand. This requires novel devices like FinFET instead of MOSFET. FinFET comes out as a multi-gate, non-planar device which controls the short channel effects, power dissipation and leakage current. 7T SRAM cell designed using the Quad Gate Stacked Nano-sheets (QG-SNS) FinFET device has been presented. The simulation methodology and the performance parameters of QG-SNS FinFET device have also been discussed. The device shows better ON current, reduced leakage current and improved subthreshold slope. The performance of the 7T SRAM cell designed using QG-SNS FinFET (7T_SNS) for read-write operation has been analyzed in regard to leakage power, propagation delay and stability. This work compares the performance of 7T_SNS SRAM cell with other SRAM cells at nano-scaled technologies. The 7T_SNS SRAM cell achieves 370% better read stability compared to 6T CMOS cell. Write static noise margin of 7T_SNS cell is almost like 6T CMOS SRAM. The leakage power and read power of 7T_SNS cell is 99.99% better as compared to 6T CMOS SRAM. Therefore, a 7T_SNS SRAM cell design having minimum power utilization and better read stability is discussed in this paper.

Hybrid Silicon Substrate FinFET-Metal Insulator Metal (MIM) Memristor Based Sense Amplifier Design for the Non-Volatile SRAM Cell

Maintaining power consumption has become a critical hurdle in the manufacturing process as CMOS technologies continue to be downscaled. The longevity of portable gadgets is reduced as power usage increases. As a result, less-cost, high-density, less-power, and better-performance memory devices are in great demand in the electronics industry for a wide range of applications, including Internet of Things (IoT) and electronic devices like laptops and smartphones. All of the specifications for designing a non-volatile memory will benefit from the use of memristors. In addition to being non-volatile, memristive devices are also characterized by the high switching frequency, low wattage requirement, and compact size. Traditional transistors can be replaced by silicon substrate-based FinFETs, which are substantially more efficient in terms of area and power, to improve the design. As a result, the design of non-volatile SRAM cell in conjunction with silicon substrate-based FinFET and Metal Insulator Metal (MIM) based Memristor is proposed and compared to traditional SRAMs. The power consumption of the proposed hybrid design has outperformed the standard Silicon substrate FinFET design by 91.8% better. It has also been reported that the delay for the suggested design is actually quite a bit shorter, coming in at approximately 1.989 ps. The proposed architecture has been made significantly more practical for use as a low-power and high-speed memory system because of the incorporation of high-K insulation at the interface of metal regions. In addition, Monte Carlo (MC) simulations have been run for the reported 6T-SRAM designs in order to have a better understanding of the device stability.

A sub-threshold 10T FinFET SRAM cell design for low-power applications

This paper presents a high-stability low-power 10 T (HSLP10T) sub-threshold SRAM cell with single-ended operations. The HSLP10T cell uses a decoupled read path, formed by a transmission gate and a dynamic inverter, thereby, resulting in read stability improvement. In addition, it employs a feedback-cutting transistor to facilitate the write operation, which increases writability. Due to single-ended operations, direct-write on complementary node, floated bitline, and use of more p-type transistors, the power consumption reduces in the proposed cell. Simulated results in the 7-nm FinFET technology indicate that at a 300 mV supply voltage, the read stability/writability of the proposed HSLP10T cell is 2.06X/1.31X as that of the conventional 6 T cell. Moreover, the dynamic/leakage power consumption is reduced by 1.82X/2.92X when compared with the conventional 6 T SRAM. The proposed HSLP10T SRAM bitcell has a layout area of 0.047 µm2, which is 1.67 × larger than the conventional 6 T SRAM. However, the highest ON-to-OFF currents ratio related to the proposed design compensates for this area overhead by connecting more number of cells to the same bitline in the columns of the SRAM array. Moreover, the minimum operation voltage is reduced by 48.28 % using proposed design compared to the conventional 6 T SRAM.