A 7T high stable and low power SRAM cell design using QG-SNS FinFET

Abstract

System on Chip (SoC) low power cache memories are in great demand. This requires novel devices like FinFET instead of MOSFET. FinFET comes out as a multi-gate, non-planar device which controls the short channel effects, power dissipation and leakage current. 7T SRAM cell designed using the Quad Gate Stacked Nano-sheets (QG-SNS) FinFET device has been presented. The simulation methodology and the performance parameters of QG-SNS FinFET device have also been discussed. The device shows better ON current, reduced leakage current and improved subthreshold slope. The performance of the 7T SRAM cell designed using QG-SNS FinFET (7T_SNS) for read-write operation has been analyzed in regard to leakage power, propagation delay and stability. This work compares the performance of 7T_SNS SRAM cell with other SRAM cells at nano-scaled technologies. The 7T_SNS SRAM cell achieves 370% better read stability compared to 6T CMOS cell. Write static noise margin of 7T_SNS cell is almost like 6T CMOS SRAM. The leakage power and read power of 7T_SNS cell is 99.99% better as compared to 6T CMOS SRAM. Therefore, a 7T_SNS SRAM cell design having minimum power utilization and better read stability is discussed in this paper.