Design of 6T FinFET SRAM cell at 7nm

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Due to the tremendous increase in power dissipation in sub-micrometer region of operation, there arises a need to design low power circuits. The continuous scaling of CMOS logic circuits is not straight forward in the sense that when CMOS devices are scaled below 16nm, short channel effects are observed. These effects increase leakage power dissipation to large extent. The memory occupies about 90% of area in any logic design. The design of memory is of main concern as there occurs parameter variations in CMOS SRAM cells when designed below 16nm. This can be solved by the replacement of CMOS with FinFET in traditional SRAM cells. In this paper, design of 6T FinFET SRAM cell is presented at 7nm technology using ASAP7 PDK and Cadence virtuoso tool. Besides, parameters like power dissipation, delay, power delay products and static noise margins are also analyzed. The simulation results showed that design of SRAM cells using FinFET can be highly efficient in comparison to CMOS SRAM cells.