High SNM 6T CNFET SRAM cell design considering nanotube diameter and transistor ratio

Abstract

As scaling down silicon semiconductor device feature size encounters great challenge nowadays, Carbon Nanotube Field Effect Transistor (CNFET) has been introduced for high stability, high performance and low power SRAM cell design as an alternative material. Static Noise Margin (SNM) is an important expression of SRAM stability. Three factors, namely supply voltage, threshold voltage and transistor ratio, determine the SRAM cell SNM. This paper proposed a high SNM 6T CNFET SRAM cell design method. By analyzing SRAM reading and writing operation and using SPICE simulation, optimal transistor ratios have been found for different nanotube diameters with 0.9v supply voltage in 32nm technology. Compared with traditional CMOS SRAM cell design, the proposed high SNM 6T CNFET SRAM cell achieved 32.03% SNM improvement, 74.02% reading power-delay product reduction and 82.03% writing power-delay product reduction.